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| Data Sheet SII0680A PCI to IDE/ATA Data Sheet Document # SiI-DS-0069-C SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Revision History: Version Rev. 0.1 Rev. 0.2 Rev. 0.3 Rev. 0.4 Rev. 0.5 Rev. 0.5A Rev 0.90 Rev. 0.91 Rev. 0.92 Rev. 0.93 Rev. 0.99 Rev. 1.0 Rev. 1.05 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. A3 Rev. B Rev. C Comment First draft (from Engineering Design Specification) Additional register definitions added Changed package type to TQFP Changed TQFP drawing: minor changes to pinout and PLL external component values Completely re-written from technical standpoint PRELIMINARY markings removed: submitted for review/comment Major Content Changes More content changes Content corrections Made Minor corrections Corrections made in preparation of releasing Rev 1.0 version including adding references to ATA/133 Final corrections made, errata added Errata for chip Revision 00, marked "680 CES", removed Changed Register defaults and Resistor Values consistent with chip Revision 01. Clarified OS support. Changed Document Number Made minor corrections and change the document name from 680 to 680A Updated part ordering number at section 4 package drawing Updated Formatting Removed confidential markings 09/24/01 11/15/01 11/29/01 01/09/02 05/16/02 02/01/05 10/24/06 11/29/06 Date 08/07/00 10/09/00 10/10/00 10/13/00 01/23/01 01/26/01 07/05/01 08/08/01 08/09/01 08/10/01 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 2 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Table of Contents 1. Overview ..............................................................................................................................................9 1.1 1.2 Key Benefits ................................................................................................................................................ 9 Features....................................................................................................................................................... 9 Overall Features ......................................................................................................................................................9 PCI Features ...........................................................................................................................................................9 ATA Features ........................................................................................................................................................10 Other Features ......................................................................................................................................................10 1.2.1 1.2.2 1.2.3 1.2.4 1.3 SiI 0680A Technical Description ............................................................................................................. 10 1.4 References ................................................................................................................................................ 10 1.5 Functional Description............................................................................................................................. 10 1.6 Functional Block Diagram ....................................................................................................................... 11 1.7 PCI Interface.............................................................................................................................................. 12 1.8 PCI Initialization ........................................................................................................................................ 12 1.9 PCI Bus Operations.................................................................................................................................. 12 1.10 PCI Configuration Space ....................................................................................................................... 13 1.11 Deviations from the Specification ........................................................................................................ 13 2.1 Device Electrical Characteristics ............................................................................................................... 14 2.2 PCI 33 MHz Timing Specifications.......................................................................................................... 15 2.3 ATA/ATAPI-6 Slew Rate Specifications ................................................................................................. 15 2.4 ATA/ATAPI-6 AC/DC Specifications ...................................................................................................... 15 2.5 Power Supply Bypass Considerations.................................................................................................. 16 3. Pin Definition.....................................................................................................................................17 3.1 SiI 0680A Pin Listing ................................................................................................................................ 17 3.2 SiI 0680A Pin Diagram.............................................................................................................................. 23 3.3 SiI 0680A Pin Descriptions ......................................................................................................................... 24 3.3.1 IDE/ATA Primary Channel.........................................................................................................................................24 3.3.2 IDE/ATA Secondary Channel ....................................................................................................................................25 3.3.3 PCI 33MHz 32-bit Section .........................................................................................................................................27 3.3.4 Miscellaneous I/O .....................................................................................................................................................29 4. Package Drawing ..............................................................................................................................32 5. ASIC Block Diagram .........................................................................................................................34 6. Clocking System ...............................................................................................................................37 7. Phased Locked Loop (PLL)..............................................................................................................38 7.1 PLL Connections ...................................................................................................................................... 38 PLL Schematic ......................................................................................................................................................38 PLL Components................................................................................................................................................39 PLL Layout Requirements ..................................................................................................................................40 7.1.1 7.1.2 7.1.3 8. Auto-Initialization..............................................................................................................................43 8.1 8.2 9.1 Auto-Initialization from FLASH ............................................................................................................... 43 Auto-Initialization from EEPROM............................................................................................................ 44 PCI Configuration Space ......................................................................................................................... 46 Device ID - Vendor ID ...........................................................................................................................................48 PCI Status - PCI Command ..................................................................................................................................48 PCI Class Code - Revision ID ...............................................................................................................................49 BIST - Header Type - Latency Timer - Cache Line Size .....................................................................................50 Base Address Register 0 .......................................................................................................................................50 Base Address Register 1 .......................................................................................................................................50 Base Address Register 2 .......................................................................................................................................51 SiI-DS-0069-C 3 9. Register Definitions ..........................................................................................................................46 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.8 Base Address Register 3 .......................................................................................................................................51 9.1.9 Base Address Register 4 .......................................................................................................................................51 9.1.10 Base Address Register 5 .....................................................................................................................................52 9.1.11 Subsystem ID - Subsystem Vendor ID................................................................................................................52 9.1.12 Expansion ROM Base Address ...........................................................................................................................53 9.1.13 Capabilities Pointer..............................................................................................................................................53 9.1.14 Max Latency - Min Grant - Interrupt Pin - Interrupt Line ....................................................................................53 9.1.15 Configuration .......................................................................................................................................................54 9.1.16 Software Data Register........................................................................................................................................54 9.1.17 Power Management Capabilities .........................................................................................................................54 9.1.18 Power Management Control + Status ..................................................................................................................55 9.1.19 PCI Bus Master - IDE0........................................................................................................................................55 9.1.20 PRD Table Address - IDE0 .................................................................................................................................56 9.1.21 PCI Bus Master - IDE1........................................................................................................................................56 9.1.22 PRD Table Address - IDE1 .................................................................................................................................56 9.1.23 Data Transfer Mode - IDE0.................................................................................................................................57 9.1.24 Data Transfer Mode - IDE1.................................................................................................................................57 9.1.25 System Configuration Status - Command ...........................................................................................................57 9.1.26 System Software Data Register...........................................................................................................................58 9.1.27 FLASH Memory Address - Command + Status ..................................................................................................58 9.1.28 FLASH Memory Data...........................................................................................................................................58 9.1.29 EEPROM Memory Address - Command + Status ..............................................................................................59 9.1.30 EEPROM Memory Data.......................................................................................................................................59 9.1.31 IDE0 Task File Timing + Configuration + Status..................................................................................................59 9.1.32 IDE0 PIO Timing..................................................................................................................................................60 9.1.33 IDE0 DMA Timing ................................................................................................................................................60 9.1.34 IDE0 UDMA Timing .............................................................................................................................................60 9.1.35 IDE1 Task File Timing + Configuration + Status..................................................................................................61 9.1.36 IDE1 PIO Timing..................................................................................................................................................61 9.1.37 IDE1 DMA Timing ................................................................................................................................................61 9.1.38 IDE1 UDMA Timing .............................................................................................................................................62 9.2 9.3 9.4 Internal Register Space - Base Address 0 ............................................................................................ 63 IDE0 Task File Register 0......................................................................................................................................63 IDE0 Task File Register 1......................................................................................................................................63 IDE0 Task File Register 2......................................................................................................................................64 IDE1 Task File Register 0......................................................................................................................................65 IDE1 Task File Register 1......................................................................................................................................65 9.2.1 9.2.2 9.3.1 9.4.1 9.4.2 Internal Register Space - Base Address 1 ............................................................................................ 64 Internal Register Space - Base Address 2 ............................................................................................ 65 9.5 Internal Register Space - Base Address 3................................................................................................ 66 9.5.1 IDE1 Task File Register 2..........................................................................................................................................66 9.6 Internal Register Space - Base Address 4................................................................................................ 67 9.6.1 PCI Bus Master - IDE0 .............................................................................................................................................67 9.6.2 PRD Table Address - IDE0.......................................................................................................................................67 9.6.3 PCI Bus Master - IDE1 .............................................................................................................................................68 9.6.4 PRD Table Address - IDE1.......................................................................................................................................68 9.7 Internal Register Space - Base Address 5................................................................................................ 69 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.7.6 9.7.7 9.7.8 9.7.9 9.7.10 9.7.11 9.7.12 9.7.13 9.7.14 9.7.15 PCI Bus Master - IDE0..........................................................................................................................................71 PRD Table Address - IDE0 ...................................................................................................................................72 PCI Bus Master - IDE1..........................................................................................................................................73 PRD Table Address - IDE1 ...................................................................................................................................73 PCI Bus Master2 - IDE0........................................................................................................................................74 PCI Bus Master2 - IDE1........................................................................................................................................75 PRD Address - IDE0 .............................................................................................................................................76 PCI Bus Master Byte Count - IDE0 .......................................................................................................................76 PRD Address - IDE1 .............................................................................................................................................76 PCI Bus Master Byte Count - IDE1 .....................................................................................................................77 FIFO Valid Byte Count and Control - IDE0..........................................................................................................77 FIFO Valid Byte Count and Control - IDE1..........................................................................................................78 System Configuration Status - Command ...........................................................................................................79 System Software Data Register...........................................................................................................................79 FLASH Memory Address - Command + Status ..................................................................................................80 SiI-DS-0069-C 4 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.16 9.7.17 9.7.18 9.7.19 9.7.20 9.7.21 9.7.22 9.7.23 9.7.24 9.7.25 9.7.26 9.7.27 9.7.28 9.7.29 9.7.30 9.7.31 9.7.32 9.7.33 9.7.34 9.7.35 9.7.36 9.7.37 9.7.38 9.7.39 9.7.40 9.7.41 9.7.42 9.7.43 9.7.44 9.7.45 9.7.46 9.7.47 9.7.48 9.7.49 9.7.50 9.7.51 9.7.52 FLASH Memory Data...........................................................................................................................................80 EEPROM Memory Address - Command + Status ..............................................................................................81 EEPROM Memory Data.......................................................................................................................................81 FIFO Port - IDE0.................................................................................................................................................82 FIFO Pointers1- IDE0 .........................................................................................................................................82 FIFO Pointers2- IDE0 .........................................................................................................................................83 FIFO Port - IDE1.................................................................................................................................................83 FIFO Pointers1- IDE1 .........................................................................................................................................84 FIFO Pointers2- IDE1 .........................................................................................................................................84 IDE0 Task File Register 0....................................................................................................................................85 IDE0 Task File Register 1....................................................................................................................................85 IDE0 Task File Register 2....................................................................................................................................86 IDE0 Read Ahead Data .......................................................................................................................................86 IDE0 Task File Register 0 - Command Buffering ................................................................................................87 IDE0 Task File Register 1 - Command Buffering ................................................................................................87 IDE0 UDMA Control.............................................................................................................................................88 IDE0 Virtual DMA/PIO Read Ahead Byte Count ..................................................................................................88 IDE0 Task File Timing + Configuration + Status..................................................................................................89 IDE0 PIO Timing..................................................................................................................................................90 IDE0 DMA Timing ................................................................................................................................................91 IDE0 UDMA Timing .............................................................................................................................................92 Test Register - IDE0 ...........................................................................................................................................93 Data Transfer Mode - IDE0.................................................................................................................................94 IDE1 Task File Register 0....................................................................................................................................94 IDE1 Task File Register 1....................................................................................................................................95 IDE1 Task File Register 2....................................................................................................................................95 IDE1 Read/Write Ahead Data ..............................................................................................................................96 IDE1 Task File Register 0 - Command Buffering ................................................................................................96 IDE1 Task File Register 1 - Command Buffering ................................................................................................97 Rserved Register .................................................................................................................................................97 IDE1 Virtual DMA/PIO Read Ahead Byte Count ..................................................................................................98 IDE1 Task File Timing + Configuration + Status..................................................................................................98 IDE1 PIO Timing..................................................................................................................................................99 IDE1 DMA Timing ..............................................................................................................................................100 IDE1 UDMA Timing ...........................................................................................................................................100 Test Register - IDE1 .........................................................................................................................................101 Data Transfer Mode - IDE1...............................................................................................................................102 10. Design for Testability ...................................................................................................................103 10.1 Test Mode Register.................................................................................................................................. 104 10.2 NAND Tree Test........................................................................................................................................ 104 10.3 Full Chip Internal Scan ............................................................................................................................ 106 10.4 PLL TEST .................................................................................................................................................. 107 10.4.1 BYPASSING the VCO ...........................................................................................................................................107 10.4.2 TESTING the VCO ................................................................................................................................................107 11. Programming Sequences.............................................................................................................108 11.1 Recommended Initialization Sequence for the SiI 0680A.................................................................... 108 11.2 ATA/ATAPI Device Initialization ............................................................................................................. 108 11.3 Initialization of Controller Channel Timing Registers.......................................................................... 109 NOTE: When using PIO to perform a data transfer, this register only instructs the controller as to whether or not it should monitor the IORDY signal when the task file data register is accessed. Any value other than 00H will cause the controller to monitor the IORDY signal.............................................................................................................................................110 11.4 Issue ATA Command............................................................................................................................... 110 11.5 IDE PIO Mode Read/Write Operation ..................................................................................................... 110 If no error, repeat the previous four steps until all data for the write command has been transferred or an error has been detected. ..........................................................................................................................................................................111 11.6 Watchdog Timer Operation..................................................................................................................... 111 11.7 IDE PIO Mode Read Ahead Operation ................................................................................................... 113 11.8 IDE MDMA/UDMA Read/Write Operation............................................................................................... 113 11.9 IDE Virtual DMA Read/Write Operation ................................................................................................. 114 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 5 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 11.9.1 Using Virtual DMA with Non-DMA Capable Devices......................................................................... 114 11.9.2 Using Virtual DMA with DMA Capable Devices ................................................................................. 116 11.10 Second PCI Bus Master Registers Usage ........................................................................................... 116 12. FLASH and EEPROM Programming Sequences........................................................................118 12.1 FLASH Memory Access........................................................................................................................... 118 12.1.1 PCI Direct Access .................................................................................................................................................118 12.2.2 Register Access ....................................................................................................................................................118 12.2 EEPROM Memory Access ....................................................................................................................... 119 13. SiI 0680A Timing Registers..........................................................................................................120 13.1 Timing Register Definition ...................................................................................................................... 120 13.2 Timing Registers Programming Suggestion ........................................................................................ 121 13.2.1 TF Timing Register Programming in Number of 33 MHz PCI clock.......................................................................121 13.2.2 PIO Timing Register Programming in Number of 33 MHz PCI clock .....................................................................121 13.2.3 DMA Timing Register Programming in Number of 33 MHz PCI clock ...................................................................121 13.2.4 UDMA Timing Register Programming in Number of 100 MHz IDE clock...............................................................121 13.2.4 UDMA Timing Register Programming in Number of 133 MHz IDE clock...............................................................121 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 6 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Table of Tables Table 2-1: Absolute Maximum Ratings......................................................................................................................................14 Table 2-2: DC Specifications ......................................................................................................................................................14 Table 2-3: PCI 33 MHz Timing Specifications ............................................................................................................................15 Table 2-4: ATA /ATAPI-6 Slew Rate Specifications ...................................................................................................................15 Table 2-5: ATA/ATAPI-6 DC Specifications ...............................................................................................................................15 Table 3-1: SiI 0680A Pin Listing .................................................................................................................................................17 Table 3-2: ATA Configuration....................................................................................................................................................30 Table 3-3: Base Address 5 Configuration..................................................................................................................................31 Table 5-1: PCI Bus Signals Group .............................................................................................................................................35 Table 5-2: IDE Channel #0 Signals Group .................................................................................................................................35 Table 5-3: IDE Channel #1 Signals Group .................................................................................................................................35 Table 5-4: SiI 0680A FLASH Memory Signals Group - Shared Signals.....................................................................................36 Table 5-5: SiI 0680A EEPROM Memory Signals Group - Shared Signals.................................................................................36 Table 5-6: SiI 0680A Test Signals Group ...................................................................................................................................36 Table 8-1: Auto-Initialization from Flash Timing .........................................................................................................................43 Table 8-2: FLASH Data Description ...........................................................................................................................................44 Table 8-3: Auto-Initialization from EEPROM Timing..................................................................................................................45 Table 8-4: Auto-Initialization from EEPROM Timing Symbols ....................................................................................................45 Table 8-5: EEPROM Data Description .......................................................................................................................................45 Table 9-1: SiI 0680A PCI Configuration Space ..........................................................................................................................46 Table 9-2: SiI 0680A Internal Register Space - Base Address 0 ..............................................................................................63 Table 9-3: SiI 0680A Internal Register Space - Base Address 1 ..............................................................................................64 Table 9-4: SiI 0680A Internal Register Space - Base Address 2 ..............................................................................................65 Table 9-5: SiI 0680A Internal Register Space - Base Address 3 ..............................................................................................66 Table 9-6: SiI 0680A Internal Register Space - Base Address 4 ..............................................................................................67 Table 9-7: SiI 0680A Internal Register Space - Base Address 5 ...............................................................................................71 Table 9-8: Software Data Byte, Base Address 5, Offset 00H .....................................................................................................72 Table 9-9: Software Data Byte, Base Address 5, Offset 10H .....................................................................................................74 Table 9-10: IDE0 Test Register Selections ...............................................................................................................................93 Table 9-11: IDE1 Test Register Selections ..............................................................................................................................101 Table 10-1: Test Mode Register Selections .............................................................................................................................104 Table 10-2: SiI 0680A NAND Tree Order .................................................................................................................................105 Table 10-2, SiI 0680A NAND Tree Order (continued) ..............................................................................................................106 Table 11-1, Physical Region Descriptor (PRD) Format ............................................................................................................117 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 7 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Table of Figures Figure 1-1: SiI 0680A Functional Block Diagram........................................................................................................................11 Figure 1-2: Address Lines During Configuration Cycle...............................................................................................................13 Figure 3-1: SiI 0680A Pin Diagram.............................................................................................................................................23 Figure 3-2: Package Drawing - 144 LQFP.................................................................................................................................32 Figure 3-3: Marking Specification - SII0680ACL144 ..................................................................................................................33 Figure 3-4: Marking Specification - SII0680ACLU144................................................................................................................33 Figure 5-1: SiI 0680A ASIC Block Diagram ................................................................................................................................34 Figure 6-1: SiI 0680A Clocking System and Test Feature Diagram ...........................................................................................37 Figure 7-1: Schematic of PLL Circuitry......................................................................................................................................38 Figure 7-2: Example Layout - Ground Plane ............................................................................................................................41 Figure 7-2: Example Layout - Power Plane ..............................................................................................................................42 Figure 8-1: Auto-Initialization from Flash Timing .......................................................................................................................43 Figure 8-2: Auto-Initialization from EEPROM Timing .................................................................................................................44 Figure 10-1: SiI 0680A Clocking System and Test Feature Diagram .......................................................................................103 Figure 10-2: Test Mode Register Programming (A1H) ..............................................................................................................104 Figure 10-3: SiI 0680A NAND Tree ..........................................................................................................................................105 Figure 10-4: PLL Test Logic ....................................................................................................................................................107 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 8 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 1. Overview The Silicon Image PCI-680 is a single-chip solution for a PCI to ATA controller. It accepts host commands through the PCI bus, processes them and transfers data between the host and ATA devices. It can be used to control two independent ATA channels: primary and secondary. Each channel has its own ATA bus and will support up to two ATA/ATAPI devices for a maximum of four devices. The PCI-680 supports up to a 133 MB/sec transfer rate exceeding that which is specified in ATA/ATAPI-6. This controller provides OEMs with an enabling solution for interfacing to storage media such as hard disk drives. For personal computer manufacturers, using the PCI-680 will differentiate them from the competition by allowing for the addition of more drives and incorporating the newest drive standards, all at a lower cost. For embedded applications, the SiI 0680A provides a high performance and cost effective interface for storage and ATAPI device support. 1.1 Key Benefits The Silicon Image PCI-680 stand-alone Ultra ATA/133 PCI to ATA host controller is the perfect single-chip solution for designs based on chipsets without an integrated ATA host controller, or designs which need to expand the number of ATA channels to accommodate the growing number of storage peripherals with ATA interface. The PCI-680 comes complete with drivers for Windows 98, Windows Millennium, Windows NT 4.0, Windows 2000, Windows XP and Linux. It is also fully operational and compatible with default IDE drivers from Microsoft. Comprehensive RAID (0, 1, 0+1) software support is also provided for Windows 98, NT 4.0, Windows Me, Windows 2000 and Windows XP. 1.2 Features 1.2.1 Overall Features * * * * * * * * * Standalone PCI to ATA host controller chip Compliant with PCI Specification, revision 2.2. Compliant with PCI IDE Controller Specification, revision 1.0. Compliant with Programming Interface for Bus Master IDE Controller, revision 1.0. Compliant with ATA/ATAPI-6 specifications. Compliant with UDMA6 ATA/133 Specification Driver support for Win98, WinME, NT4, Win2K and XP.(IDE and RAID including Linux IDE support) Supports up to 4Mbit external FLASH or EPROM for BIOS expansion. Supports an external EEPROM, FLASH or serial EPROM for programmable subsystem vendor ID and subsystem product ID. * Supports all necessary test requirements for WHQL. * Supports the Microsoft driver protocols for PIO and bus master DMA operations. * * Supports DMA transfers across the 64K physical boundary and supports transfer sizes >64K (up to 2TB) * Provides virtual DMA support for efficient PCI bus utilization for PIO transfers * Fabricated in a 0.35 CMOS process with a 3.3 volt core and 5 volt tolerant I/Os. * Available in a 144-pin LQFP package. PCI Features * Supports PCI 33 MHz with 32-bit data. * Supports PCI PERR and SERR reporting. * Supports PCI bus master operations: Memory Read, Memory Read Multiple, and Memory Write. * Supports PCI bus target operations: Configuration Read, Configuration Write, I/O Read, I/O Write, Memory Read, Memory Write, Memory Read Line (Memory Read), Memory Read Multiple (Memory Read), Memory Write and Invalidate (Memory Write). * Supports byte alignment for odd-byte PCI address access. * Supports jumper configurable PCI class code. * Supports programmable and EEPROM, FLASH and EPROM loadable PCI class code. * Supports memory space (BAR5) accesses. Supports IDE native mode (non-legacy) functions only. 1.2.2 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 9 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 1.2.3 ATA Features * Supports two independent ATA channels. * Supports ATA 133. * Supports full speed burst transfers on the ATA bus. * Supports software-controlled ATA bus tri-state. * Supports device specific timing registers. * Supports device read-ahead and write-ahead capability under Virtual DMA. Other Features * Features one 256-byte FIFO (32-bit x 64 deep) per IDE channel for host reads and writes. * Features ATA to PCI interrupt masking. * Features command buffering from the PCI to ATA. * Features Virtual DMA: Bus master transfer on the PCI bus and PIO transfer on the ATA bus. * Features Watch Dog Timer for fault resiliency. 1.2.4 1.3 PCI-680 Technical Description The PCI-680A is available in a 144-pin LQFP (Thin Quad Flat Package) including more ground pins in order to accommodate the new higher data transfer rate specified in the ATA/ATAPI-6 specification. The chip has an internal phase lock loop that will provide the 100/133MHz (selectable) internal clock, allowing a data transfer rate of 100/133MB/sec (selectable) on ATA interface. A built-in 80-pin cable detector provides users the ability to determine whether a cable can support the latest Ultra ATA/100/133 (selectable) transfer rate. The PCI-680 is capable of supporting Native mode, external BIOS, Enhanced IDE mode (ultra DMA and multiword DMA mode) and PIO mode. 1.4 References For more details about the ATA technology, the reader is referred to the following industry specifications: * ATA/ATAPI-6 (at time of publication, ATA/ATAPI-6 has not been formally approved) * PCI Local Bus Specification Revision 2.2 * Advanced Power Management Specification Revision 1.0 * PCI IDE Controller Specification Revision 1.0 * Programming Interface for Bus Master IDE Controller, Revision 1.0 1.5 Functional Description PCI-680 is more than a PCI-to-ATA bridge chip that transfers data between the PCI bus and storage media (e.g hard disk drive, etc) over the ATA bus. As a host controller, it also performs functions associated with the host, such as storing configuration information, and processing data for errors. The PCI-680 can be described in the following functional blocks: * PCI Interface. Provides the interface to any system that has a PCI bus. Instructions and system clocks are based on this interface. * ATA Interface. Two separate channels (Primary and Secondary) to access storage media such as hard disk drives, CD-ROM's etc. * Controller Interface. Additional hardware interface for controlling and configuring the Host Controller. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 10 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 1.6 Functional Block Diagram PCI DM A transf er counter PCI State M achi ne 32 bi ts PCI Figure 1-1: SiI 0680A Functional Block Diagram (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 11 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 1.7 PCI Interface The PCI-680 PCI interface is compliant with the PCI Local Bus Specification (Revision 2.2). PCI stands for Peripheral Component Interconnect, a high-performance and robust interconnect bus that provides a processor-independent data path between the CPU and high-speed peripherals. The PCI Specification is monitored by the PCI Special Interest Group (PCISIG). The PCI-SIG is an unincorporated association of members of the microcomputer industry created to monitor and enhance the development of PCI architecture and is governed by PCI-SIG bylaws (HTTP://www.pcisig.com/). The PCI-680 can act as a PCI master and a PCI slave, and contains the PCI-680 PCI configuration space and internal registers. When the PCI-680 needs to access shared memory, it becomes the bus master of the PCI bus and completes the memory cycle without external intervention. In the mode when it acts as a bridge between the PCI bus and the IDE/ATA bus it will behave as a PCI slave. 1.8 PCI Initialization Generally, when a system initializes a module containing a PCI device, the configuration manager reads the configuration space of each PCI device on the PCI bus. Hardware signals select a specific PCI device based on a bus number, a slot number, and a function number. If a device that is addressed (via signal lines) responds to the configuration cycle by claiming the bus, then that function's configuration space is read out from the device during the cycle. Since any PCI device can be a multifunction device, every supported function's configuration space needs to be read from the device. Based on the information read, the configuration manager will assign system resources to each supported function within the device. Sometimes new information needs to be written into the function's configuration space. This is accomplished with a configuration write cycle. 1.9 PCI Bus Operations PCI-680 behaves either as a PCI master or a PCI slave device at any time and switches between these modes as required during device operation. As a PCI slave, the PCI-680 responds to the following PCI bus operations: * * * * * * I/O Read I/O Write Configuration Read Configuration Write Memory Read Memory Write All other PCI cycles are ignored by the PCI-680. As a PCI master, the PCI-680 generates the following PCI bus operations: * * * * Memory Read Multiple Memory Read Line Memory Read Memory Write (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 12 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 1.10 PCI Configuration Space This section describes how the PCI-680 implements the required PCI configuration register space. The intent is to provide an appropriate set of configuration registers that satisfy the needs of current and anticipated system configuration mechanisms, without specifying those mechanisms or otherwise placing constraints on their use. These registers allow for: * * * Full device relocation (including interrupt binding) Installation, configuration, and booting without user interventions System address map construction by device-independent software Bit Number 31 11 10 87 21 Bit 0 Number Don't Care 3-Bit Function Number 6-Bit Register Number 2-Bit Type Number Figure 1-2: Address Lines During Configuration Cycle PCI-680 only responds to Type 0 configuration cycles. Type 1 cycles, which pass a configuration request on to another PCI bus, are ignored. The address phase during a PCI-680 configuration cycle indicates the function number and register number being addressed which can be decoded by observing the status of the address lines AD[31:0]. The value of the signal lines AD[7:2] during the address phase of configuration cycles selects the register of the configuration space to access. Valid values are between 0 and 15, inclusive. Accessing registers outside this range results in an all-0s value being returned on reads, and no action being taken on writes. The Class Code register contains the Class Code, Sub-Class Code, and Register-Level Programming Interface registers. All writable bits in the configuration space are reset to 0 by the hardware reset, PCI RESET (RST#) asserted. After reset, PCI680 is disabled and will only respond to PCI configuration write and PCI configuration read cycles. 1.11 Deviations from the Specification The PCI-680 product has been developed and tested to the specification listed in this document. As a result of testing and customer feedback, we may become aware of deviations to the specification that could affect the component's operation. To ensure awareness of these deviations by anyone considering the use of the PCI-680, we will include them in this document. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 13 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 2. Electrical Characteristics 2.1 Device Electrical Characteristics Specifications are for temperature range, 0oC to 70oC, unless otherwise specified. Symbol VDDH VIN IOUT TSTG Parameter Supply Voltage Input Voltage DC Output Current Storage Temperature Ratings 3.6 -0.3 ~ 6.0 16 -65 ~ 150 Unit V V mA o C Table 2-1: Absolute Maximum Ratings Symbol Parameter Condition Type Min VDD Supply Voltage Supply Current (See Sec. 2.5) Input High Voltage Quiescent Operating VIL Input Low Voltage V+ VVH IIH IIL VOH VOL IOZ Input High Voltage Input Low Voltage Hysteresis Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage 3-State Leakage Current VIN = VDD VIN = VSS 3.3V PCI Non-PCI 3.3V PCI Non-PCI Schmitt Schmitt Schmitt 3.0 0.5xVDD 2.0 0.5 0.4 -10 -10 2.4 -10 Limits Typ 3.3 250 350 1.8 0.9 Max 3.6 0.3xVDD 0.8 2.3 10 10 0.4 10 V V V A A V V A V V V mA Unit IDD VIH Table 2-2: DC Specifications (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 14 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 2.2 PCI 33 MHz Timing Specifications Symbol Parameter Limits Min TVAL TVAL (PTP) TON TOFF TSU TSU (PTP) TH CLK to Signal Valid - Bussed Signals CLK to Signal Valid - Point to Point Float to Active Delay Active to Float Delay Input Setup Time - Bussed Signals Input Setup Time - Point to Point Input Hold Time 2.0 2.0 2.0 7.0 10.0 0.0 Max 11.0 11.0 28.0 ns ns ns ns ns ns ns Unit Table 2-3: PCI 33 MHz Timing Specifications 2.3 ATA/ATAPI-6 Slew Rate Specifications Symbol Parameter Condition Limits Min SRISE Output Slew Rate - Rising Output Slew Rate - Falling SFALL Refer to ATA Specification for specific test condition requirements Refer to ATA Specification for specific test condition requirements 0.4 0.4 Max 1 1 V/ns V/ns Unit Table 2-4: ATA /ATAPI-6 Slew Rate Specifications 2.4 ATA/ATAPI-6 AC/DC Specifications Symbol Parameter Condition Limits Min IOL IOH V+ VVOH VOL Output Voltage Low Output Sink Current Output Source Current Low-to-High Input Threshold High-to-Low Input Threshold Output Voltage High -6 mA < IOUT < 3 mA IOUT = 6 mA Table 2-5: ATA/ATAPI-6 DC Specifications 4 400 1.5 1.0 VDD 0.51 Max 2.0 1.5 VDD+ 0.3 0.51 mA A V V V V Unit (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 15 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 2.5 Power Supply Bypass Considerations It is recommended that a 4-layer board (minimum) with internal Power and Ground Planes be used when i integrating the SiI 0680A . Good high-speed layout techniques should be used and proper power supply bypassing is essential. Both bulk and local (high frequency) bypass capacitors should be used. Bulk bypassing is intended to reduce the voltage noise (droop) induced by changes in load current and the inductance in the power distribution system (wires and/or etch). Since the currents vary greatly from no activity to worst case data patterns, a significant amount of capacitance is required. All bypass capacitors should be connected to the power and ground plane with a low inductance connection (short, wide traces connecting component pad to plane). The bulk bypass capacitor(s) should have good high frequency characteristics. A capacitor with low ESR (Equivalent Series Resistance) should be used. It should be located close to the source of +3.3V (output pin of regulator or connector pin for off board regulators). The following minimum values are recommended: Low ESR Tantalum - 100uF Low ESR Aluminum Electrolytic - 600uF Local high frequency 0bypass should also be implemented. Capacitors should be located on all four sides of the chip close to the VDD/VSS pins. Three caps per side are recommended (12 total). Additional capacitors (x6) should be distributed evenly around the board area. The following capacitor is recommended for local bypass: Ceramic X7R Dielectric - 0.01uF For a slight improvement in high frequency impedance of the bypass capacitors, two capacitors in parallel can be used for Local Bypass. The paired caps must be located as close as possible to each other. The following values are recommended for the capacitor pairs: Ceramic X7R Dielectric - 0.1uF Ceramic X7R Dielectric - 1000pF (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 16 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 3. Pin Definition 3.1 PCI-680 Pin Listing This section describes the pin-out of the SiI 0680A PCI-to-ATA host controller ASIC. Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VSS Pin Name Type GND PWR Analog Analog Analog GND I I/O I/O I/O I/O I/O I/O I/O I/O PWR GND I/O I/O Drive ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer Internal Resistor PD - 20k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PD - 100k PU - 100k PU - 100k Ground Description PLL_VDD PLL_CPBIAS PLL_VCOBIAS PLL_LOOPFLT PLL_GND TEST_MODE IDE0_DD00 IDE0_DD01 IDE0_DD02 IDE0_DD03 IDE0_DD04 IDE0_DD05 IDE0_DD06 IDE0_DD07 VDD VSS IDE0_DD08 IDE0_DD09 PLL 3.3 Volt Power PLL Charge Pump Bias PLL VCO Bias PLL Loop Filter PLL Ground ASIC Test Mode Enable IDE #0 Data Bus bit 0 / FLASH memory address bit 18 IDE #0 Data Bus bit 1 / FLASH memory address bit 17 IDE #0 Data Bus bit 2 / FLASH memory address bit 16 IDE #0 Data Bus bit 3 / FLASH memory address bit 15 IDE #0 Data Bus bit 4 / FLASH memory address bit 14 IDE #0 Data Bus bit 5 / FLASH memory address bit 13 IDE #0 Data Bus bit 6 / FLASH memory address bit 12 IDE #0 Data Bus bit 7 / FLASH memory address bit 11 3.3 Volt Power Ground IDE #0 Data Bus bit 8 / FLASH memory address bit 10 IDE #0 Data Bus bit 9 / FLASH memory address bit 9 Table 3-1: SiI 0680A Pin Listing (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 17 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin # 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin Name IDE0_DD10 IDE0_DD11 IDE0_DD12 IDE0_DD13 IDE0_DD14 IDE0_DD15 VDD VSS IDE0_CS0_N IDE0_CS1_N IDE0_DA0 IDE0_DA1 IDE0_DA2 IDE0_DIOR_N IDE0_DIOW_N IDE0_DMACK_N VDD VSS IDE0_CBLID_N IDE0_INTRQ IDE0_IORDY IDE0_AT_REXT IDE0_DMARQ IDE0_RST_N Type I/O I/O I/O I/O I/O I/O PWR GND I/O I/O I/O I/O I/O I/O I/O I/O PWR GND I-Schmitt I-Schmitt I-Schmitt Analog I-Schmitt I/O Drive ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer 12 mA 12 mA 12 mA 12 mA 12 mA ATA Buffer ATA Buffer ATA Buffer 12 mA Internal Resistor PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PD - 100k PU - 100k PD - 100k Description IDE #0 Data Bus bit 10 / FLASH memory address bit 8 IDE #0 Data Bus bit 11 / FLASH memory address bit 7 IDE #0 Data Bus bit 12 / FLASH memory address bit 6 IDE #0 Data Bus bit 13 / FLASH memory address bit 5 IDE #0 Data Bus bit 14 / FLASH memory address bit 4 IDE #0 Data Bus bit 15 / FLASH memory address bit 3 3.3 Volt Power Ground IDE #0 Chip Select / memory read strobe IDE #0 Chip Select / memory write strobe FLASH FLASH IDE #0 Device Address / FLASH memory address bit 2 IDE #0 Device Address / FLASH memory address bit 1 IDE #0 Device Address / FLASH memory address bit 0 IDE #0 Device I/O Read IDE #0 Device I/O Write IDE #0 DMA Acknowledge 3.3 Volt Power Ground IDE #0 Cable ID IDE #0 Interrupt Request IDE #0 I/O Ready IDE #0 External Bias Circuit IDE #0 DMA Request IDE #0 Reset Table 3-1: SiI 0680A Pin Listing (continued) (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 18 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin # 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pin Name IDE1_DD00 IDE1_DD01 IDE1_DD02 IDE1_DD03 IDE1_DD04 IDE1_DD05 IDE1_DD06 VDD VSS IDE1_DD07 IDE1_DD08 IDE1_DD09 IDE1_DD10 IDE1_DD11 IDE1_DD12 IDE1_DD13 IDE1_DD14 VDD VSS IDE1_DD15 IDE1_CS0_N IDE1_CS1_N IDE1_DA0 IDE1_DA1 IDE1_DA2 Type I/O I/O I/O I/O I/O I/O I/O PWR GND I/O I/O I/O I/O I/O I/O I/O I/O PWR GND I/O I/O I/O I/O I/O I/O ATA Buffer 12 mA 12 mA 12 mA 12 mA 12 mA Drive ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer ATA Buffer Internal Resistor PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PD - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k PU - 100k Description IDE #0 Data Bus bit 0 / FLASH memory data bit 0 IDE #0 Data Bus bit 1 / FLASH memory data bit 1 IDE #0 Data Bus bit 2 / FLASH memory data bit 2 IDE #0 Data Bus bit 3 / FLASH memory data bit 3 IDE #0 Data Bus bit 4 / FLASH memory data bit 4 IDE #0 Data Bus bit 5 / FLASH memory data bit 5 IDE #0 Data Bus bit 6 / FLASH memory data bit 6 3.3 Volt Power Ground IDE #0 Data Bus bit 7 / FLASH memory data bit 7 IDE #1 Data Bus IDE #1 Data Bus IDE #1 Data Bus IDE #1 Data Bus IDE #1 Data Bus IDE #1 Data Bus IDE #1 Data Bus 3.3 Volt Power Ground IDE #1 Data Bus IDE #1 Chip Select / EEPROM SCLK IDE #1 Chip Select / EEPROM SDAT IDE #1 Device Address IDE #1 Device Address IDE #1 Device Address Table 3-1: SiI 0680A Pin Listing (continued) (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 19 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin # 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Pin Name IDE1_DIOR_N IDE1_DIOW_N IDE1_CBLID_N VDD VSS IDE1_DMACK_N IDE1_INTRQ IDE1_IORDY IDE1_AT_REXT IDE1_DMARQ IDE1_RST_N JP PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 VDD VSS PCI_AD25 PCI_AD24 PCI_CBE3 PCI_IDSEL PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 VDD VSS Type I/O I/O I-Schmitt PWR GND I/O I-Schmitt I-Schmitt Analog I-Schmitt I/O I I/O I/O I/O I/O I/O I/O PWR GND I/O I/O I/O I I/O I/O I/O I/O I/O PWR GND Drive ATA Buffer ATA Buffer ATA Buffer 12 mA PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI Internal Resistor PU - 100k PD - 100k PU - 100k PD - 100k PU - 20k Description IDE #1 Device I/O Read IDE #1 Device I/O Write IDE #1 Cable ID 3.3 Volt Power Ground IDE #1 DMA Acknowledge IDE #1 Interrupt Request IDE #1 I/O Ready IDE #1 External Bias Circuit IDE #1 DMA Request IDE #1 Reset IDE Configuration Jumper PCI Address/Data PCI Address/Data PCI Address/Data PCI Address/Data PCI Address/Data PCI Address/Data 3.3 Volt Power Ground PCI Address/Data PCI Address/Data PCI Command/Byte Enable PCI ID Select PCI Address/Data PCI Address/Data PCI Address/Data PCI Address/Data PCI Address/Data 3.3 Volt Power Ground Table 3-1: SiI 0680A Pin Listing (continued) (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 20 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin # 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Pin Name PCI_AD18 PCI_AD17 PCI_AD16 PCI_CBE2 PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N VDD VSS PCI_STOP_N PCI_PERR_N PCI_SERR_N PCI_PAR PCI_CBE1 PCI_AD15 PCI_AD14 PCI_AD13 VDD VSS PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD09 PCI_AD08 PCI_CBE0 PCI_AD07 PCI_AD06 VDD VSS PCI_AD05 Type I/O I/O I/O I/O I/O I/O I/O I/O PWR GND I/O I/O OD I/O I/O I/O I/O I/O PWR GND I/O I/O I/O I/O I/O I/O I/O I/O PWR GND I/O Drive PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI Internal Resistor Description PCI Address/Data PCI Address/Data PCI Address/Data PCI Command/Byte Enable PCI Frame PCI Initiator Ready PCI Target Ready PCI Device Select 3.3 Volt Power Ground PCI Stop PCI Parity Error PCI System Error PCI Parity PCI Command/Byte Enable PCI Address/Data PCI Address/Data PCI Address/Data 3.3 Volt Power Ground PCI Address/Data PCI Address/Data PCI Address/Data PCI Address/Data PCI Address/Data PCI Command/Byte Enable PCI Address/Data PCI Address/Data 3.3 Volt Power Ground PCI Command/Byte Enable Table 3-1: SiI 0680A Pin Listing (continued) (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 21 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin # 131 132 133 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name PCI_AD04 PCI_AD03 PCI_AD02 PCI_AD02 PCI_AD01 PCI_AD00 PCI_REQ_N PCI_GNT_N PCI_INTA_N BA5_EN PCI_CLK PCI_RST_N SCAN_EN MEM_CS_N VDD Type I/O I/O I/O I/O I/O I/O T I OD I I I-Schmitt I I/O PWR Drive PCI PCI PCI PCI PCI PCI PCI PCI 4 mA Internal Resistor PD - 20k Description PCI Command/Byte Enable PCI Command/Byte Enable PCI Command/Byte Enable PCI Command/Byte Enable PCI Command/Byte Enable PCI Command/Byte Enable PCI Bus Request PCI Bus Grant PCI Interrupt Base Address 5 Enable Jumper PCI Clock PCI Reset Internal Scan Enable Memory Chip Select 3.3 Volt Power Table 3-1: SiI 0680A Pin Listing (continued) Pin Type I I-Schmitt O T I/O OD Pin Description Input Pin with LVTTL Thresholds Input Pin with Schmitt Trigger Output Pin Tri-state Output Pin Bidirect Pin Open Drain Output Pin (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 22 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 3.2 PCI-680 Pin Diagram The PCI-680 pin diagram is shown in Figure 3-1. VDD PCI_DEVSEL_N PCI_TRDY_N PCI_IRDY_N PCI_FRAME_N PCI_CBE2 PCI_AD16 PCI_AD17 PCI_AD18 VSS VDD PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_IDSEL PCI_CBE3 PCI_AD24 PCI_AD25 VSS VDD PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 JP IDE1_RST_N IDE1_DMARQ IDE1_AT_REXT IDE1_IORDY IDE1_INTRQ IDE1_DMACK_N VSS 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 EEPROM SDAT EEPROM SCLK VSS PCI_STOP_N PCI_PERR_N PCI_SERR_N PCI_PAR PCI_CBE1 PCI_AD15 PCI_AD14 PCI_AD13 VDD VSS PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD09 PCI_AD08 PCI_CBE0 PCI_AD07 PCI_AD06 VDD VSS PCI_AD05 PCI_AD04 PCI_AD03 PCI_AD02 PCI_AD01 PCI_AD00 PCI_REQ_N PCI_GNT_N PCI_INTA_N BA5_EN PCI_CLK PCI_RST_N SCAN_EN MEM_CS_N VDD 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 SiI 0680 Top View 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VDD IDE1_CBLID_N IDE1_DIOW_N IDE1_DIOR_N IDE1_DA2 IDE1_DA1 IDE1_DA0 IDE1_CS1_N IDE1_CS0_N IDE1_DD15 VSS VDD IDE1_DD14 IDE1_DD13 IDE1_DD12 IDE1_DD11 IDE1_DD10 IDE1_DD09 IDE1_DD08 IDE1_DD07 VSS VDD IDE1_DD06 IDE1_DD05 IDE1_DD04 IDE1_DD03 IDE1_DD02 IDE1_DD01 IDE1_DD00 IDE0_RST_N IDE0_DMARQ IDE0_AT_REXT IDE0_IORDY IDE0_INTRQ IDE0_CBLID_N VSS EEPROM SDAT EEPROM SCLK FLASH DATA[07] FLASH FLASH FLASH FLASH FLASH FLASH FLASH DATA[06] DATA[05] DATA[04] DATA[03] DATA[02] DATA[01] DATA[00] Figure 3-1: PCI-680 Pin Diagram FLASH RD_N FLASH WR_N FLASH ADDR[02] FLASH ADDR[01] FLASH ADDR[00] ADDR[18] ADDR[17] ADDR[16] ADDR[15] ADDR[14] ADDR[13] ADDR[12] ADDR[11] FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH ADDR[10] ADDR[09] ADDR[08] ADDR[07] ADDR[06] ADDR[05] ADDR[04] ADDR[03] VSS PLL_VDD PLL_CPBIAS PLL_VCOBIAS PLL_LOOPFLT PLL_GND TEST_MODE IDE0_DD00 IDE0_DD01 IDE0_DD02 IDE0_DD03 IDE0_DD04 IDE0_DD05 IDE0_DD06 IDE0_DD07 VDD VSS IDE0_DD08 IDE0_DD09 IDE0_DD10 IDE0_DD11 IDE0_DD12 IDE0_DD13 IDE0_DD14 IDE0_DD15 VDD VSS IDE0_CS0_N IDE0_CS1_N IDE0_DA0 IDE0_DA1 IDE0_DA2 IDE0_DIOR_N IDE0_DIOW_N IDE0_DMACK_N VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 23 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 3.3 PCI-680 Pin Descriptions 3.3.1 IDE/ATA Primary Channel IDE0 Disk Data Bus Pin Names: IDE0_DD[15..0] Pin Numbers: 25, 24, 23, 22, 21, 20, 19, 18, 15, 14, 13, 12, 11, 10, 9, 8 Disk Data bits 0 through 15 are the 16-bit bi-directional data bus which connects to the ATA device(s). IDE0_DD[15:0] are data signals to the primary Channel. IDE0_DD[7:0] defines the low byte while IDE0_DD[15:8] defines the high byte of this 16bit data register. The data bus is normally in a high impedance state and is driven by the SiI 0680A during the IDE0_DIOW_N command pulse in either single/multi-word DMA mode, or valid at every edge of IDE0_DIOR_N (HSTROBE) or IDE0_IORDY (DSTROBE) in Ultra DMA mode. IDE0_DD[7] is a multifunction pin which allows a host to recognize the absence of an ATA/ATAPI device at power-up. It is recommended that a 10k pull-down resistor be connected to this pin. IDE0 Chip Select Pin Names: IDE0_CS0_N; IDE0_CS1_N Pin Numbers: 28, 29 These are the chip select signals from the host used to select the Command Block or Control Block registers. When IDE0_DMACK_N is asserted, IDE0_CS0_N and IDE0_CS1_N shall be negated and transfers shall be 16 bits wide. IDE0 Disk Address Pin Names: IDE0_DA[2..0] Pin Numbers: 32, 31, 30 Disk Address bits 0 through 2 are normally outputs to the ATA connector selecting the register in the drive's Command Block register. IDE0_DA[2:0] sends address signals to the primary channel. These address signals are decoded from the PCI_AD[2:0] and PCI_CBE[3:0] inputs. IDE0 Disk I/O Read Pin Name: IDE0_DIOR_N Pin Number: 33 Primary Channel Disk I/O Read is an active low output which enables data to be read from the drive. The duration and repetition rate of IDE0_DIOR_N cycles is determined by SiI 0680A programming. IDE0_DIOR_N to the primary channel is driven high when inactive. This signal is defined as HSTROBE in Ultra DMA write mode to write data to the primary channel drive. This signal is also defined as primary channel HDMARDY_N in Ultra DMA read mode. IDE0 Disk I/O Write Pin Name: IDE0_DIOW_N Pin Number: 34 Primary Channel Disk I/O Write is an active low output that enables data to be written to the drive. The duration and repetition of IDE0_DIOW_N cycles is determined by SiI 0680A Programming. IDE0_DIOW_N to the primary channel is driven high when inactive. This signal is defined as primary channel STOP in ultra DMA mode. IDE0 DMA Acknowledge Pin Name: IDE0_DMACK_N Pin Number: 35 This signal is normally used by the SiI 0680A in response to IDE0_DMARQ to either acknowledge that the primary channel is ready to accept data, or that data is available. This signal is also used to write CRC code to the primary channel drive at the end of each Ultra DMA burst transfer. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 24 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. IDE0 Cable Detect Pin Names: IDE0_CBLID_N Pin Numbers: 38 IDE0_CBLID_N (Cable Detect) determines the type of cable attached to the primary channel. In general, a low on this pin indicates that an 80 conductor cable is attached. A high indicates that a 40 conductor cable is attached. Refer to the ATA/ATAPI-6 Specification for complete details. IDE0 Interrupt Request Pin Name: IDE0_INTRQ Pin Number: 39 Primary channel interrupt request is an input signal used to generate the PCI_INTA_N output. This input should have a 10k pull-down resistor connected to it. IDE0 I/O Ready Pin Name: IDE0_IORDY Pin Number: 40 The Primary channel drive I/O ready is an active high input. It indicates that the IDE/ATA disk drive has completed the current command cycle. A 4.7k pull-up resistor is recommended. This signal is defined as DSTROBE in Ultra DMA read mode to read data from the currently selected drive to the primary channel. This signal is also defined as DDMARDY_N in Ultra DMA write mode. IDE0 External Bias Circuit Pin Name: IDE0_AT_REXT Pin Number: 41 IDE0_AT_REXT is an analog pin for connection to an external bias circuit. Connect (in parallel) an 1.74K, 1% resistor and an 820 pF, 5% capacitor between this pin and ground. This pin is sensitive to noise and must be routed carefully. Keep the trace length on this pin as short as possible and away from any sources of noise. IDE0 DMA Request Pin Name: IDE0_DMARQ Pin Number: 42 This signal is used in a handshake manner with IDE0_DMACK_N, and shall be asserted high by the currently selected drive attached to the primary IDE/ATA Channel when it is ready to transfer data to or from the host. This pin should have a 5.6 K pull-down resistor connected to it. IDE0 Disk Reset Pin Name: IDE0_RST_N Pin Number: 43 IDE0 Disk Reset is an active low output which signals the IDE/ATA drive to initialize its control register. IDE0_RST_N is a buffered version of the PCI_RST_N input. It can also be generated by programming the SiI 0680A register and connects directly to the ATA connector. IDE0_RST_N asserts reset to the primary IDE/ATA channel. 3.3.2 IDE/ATA Secondary Channel IDE1 Disk Data Bus Pin Names: IDE1_DD[15..0] Pin Numbers: 63, 60, 59, 58, 57, 56, 55, 54, 53, 50, 49, 48, 47, 46, 45, 44 Disk Data bits 0 through 15 are the 16-bit bi-directional data bus, which connects to the IDE/ATA device(s). IDE1_DD[15:0] are data signals to the secondary channel. IDE1_DD[7:0] defines the low data byte while IDE1_DD[15:8] defines the high data byte of this 16-bits data register. The data bus is normally in a high impedance state and is driven by the SiI 0680A during the IDE1_DIOW_N command pulse in either single/multi-word DMA mode, or valid at every edge of IDE1_DIOR_N (HSTROBE) or IDE1_IORDY (DSTROBE) in Ultra DMA mode. IDE1_DD07 is a multifunction pin, which allows a host to recognize the (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 25 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. absence of an ATA/ATAPI device at power-up. It is recommended that a 10k pull-down resistor is recommended to be connected to this pin. IDE1 Chip Select Pin Names: IDE1_CS0_N; IDE1_CS1_N Pin Numbers: 64, 65 These are the chip select signals from the host used to select the Command Block or Control Block registers. When IDE1_DMACK_N is asserted, IDE1_CS0_N and IDE1_CS1_N shall be negated and transfers shall be 16 bits wide. IDE1 Disk Address Pin Names: IDE1_DA[2..0] Pin Numbers: 68, 67, 66 Disk Address bits 0 through 2 are normally outputs to the ATA connector to select the register in the drive's Command Block register. IDE1_DA [2:0] sends address signals to the secondary channel. These address signals are decoded from the PCI_AD[2:0] and PCI_CBE[3:0] inputs. IDE1 Disk I/O Read Pin Name: IDE1_DIOR_N Pin Number: 69 This is an active low output which enables data to be read from the drive. The duration and repetition rate of IDE1_DIOR_N cycles is determined by programming the SiI 0680A PIO timing registers. IDE1_DIOR_N to the secondary channel is driven high when inactive. This signal is defined as HSTROBE in Ultra DMA write mode to write data to the secondary channel drive. This signal is also defined as secondary channel HDMARDY_N in Ultra DMA read mode. IDE1 Disk I/O Write Pin Name: IDE1_DIOW_N Pin Number: 70 This is an active low output that enables data to be written to the drive. The duration and repetition rate of IDE1_DIOW_N cycles is determined by programming the SiI 0680A PIO timing registers. IDE1_DIOW_N to the Secondary channel is driven high when inactive. This signal is also defined as secondary channel STOP in Ultra DMA mode. IDE1 Cable Detect Pin Names: IDE1_CBLID_N Pin Number: 71 IDE1_CBLID_N (Cable Detect) determines the type of cable attached to the primary channel. In general, a low on this pin indicates that a 40 conductor cable is attached. A high indicates that an 80 conductor cable is attached. Refer to the ATA/ATAPI-6 Specification for complete details. IDE1 DMA Acknowledge Pin Name: IDE1_DMACK_N Pin Number: 74 This signal is normally used by the SiI 0680A in response to IDE1_DMARQ to either acknowledge that the secondary channel is ready to accept data, or that data is available. This signal is also used to write CRC code to the secondary channel drive at the end of each Ultra DMA burst transfer. IDE1 Interrupt Request Pin Name: IDE1_INTRQ Pin Number: 75 Primary channel interrupt request is an input signal used to generate the PCI_INTA_N output. This input should have a 10k pull-down resistor connected to it. IDE1 I/O Ready (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 26 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin Name: IDE1_IORDY Pin Number: 76 The Secondary Channel Drive Channel's Initiator Ready is an active high input. It indicates that the ATA disk drive has completed the current command cycle. A 4.7K pull-up resistor is recommended. This signal is defined as DSTROBE in Ultra DMA read mode to read data from the currently selected drive attached to the secondary channel. This signal is also defined as DDMARDY_N in Ultra DMA write mode. IDE1 External Bias Circuit Pin Name: IDE1_AT_REXT Pin Number: 77 IDE1_AT_REXT is an analog pin for connection to an external bias circuit. Connect (in parallel) an1.74K, 1% resistor and an 820 pF, 5% capacitor between this pin and ground. This pin is sensitive to noise and must be routed carefully. Keep the trace length on this pin as short as possible and away from any sources of noise. IDE1 DMA Request Pin Name: IDE1_DMARQ Pin Number: 78 This signal is used in a handshake manner with IDE1_DMACK_N and shall be asserted high by the currently selected drive attached to the secondary IDE/ATA channel when it is ready to transfer data to or from the host. . This pin should have a 5.6 K pull-down resistor connected to it. IDE1 Disk Reset Pin Name: IDE1_RST_N Pin Number: 79 Disk Reset is an active low output which signals the IDE/ATA drive to initialize its control register. IDE1_RST_N is a buffered version of the PCI_RST_N input. It can also be generated by programming the SiI 0680A register, and connects directly to the ATA connector. IDE1_RST_N asserts reset to the secondary ATA channel. 3.3.3 PCI 33MHz 32-bit Section PCI Address and Data Pin Names: PCI_AD[31..0] Pin Numbers: 81~86, 89, 90, 93~97, 100~102, 115~117, 120~124, 126, 127, 130~135 Address and Data buses are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. PCI supports both read and write bursts. The address phase is the first clock cycle in which PCI_FRAME_N signal is asserted. During the address phase, PCI_AD[31:0] contain a physical address (32 bits). For I/O, this can be a byte address. For configuration and memory it is a DWORD address. During data phases, PCI_AD[7:0] contain the least significant byte (LSB) and PCI_AD[31:24] contain the most significant byte (MSB). Write data is stable and valid when PCI_IRDY_N is asserted; read data is stable and valid when PCI_TRDY_N is asserted. Data is transferred during those clocks where both PCI_IRDY_N and PCI_TRDY_N are asserted. PCI Command and Byte Enables Pin Names: PCI_CBE[3..0] Pin Numbers: 91, 103, 114, 125 Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, PCI_CBE[3:0]_N define the bus command. During the data phase, PCI_CBE[3:0]_N are used as Byte Enables. Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. PCI ID Select Pin Name: PCI_IDSEL Pin Number: 92 This signal is used as a chip select during configuration read and write transactions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 27 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. PCI Frame Cycle Pin Name: PCI_FRAME_N Pin Number: 104 Cycle Frame is driven by the current master to indicate the beginning and duration of an access. PCI_FRAME_N is asserted to indicate that a bus transaction is beginning. While PCI_FRAME_N is asserted, data transfers continue. When PCI_FRAME_N is de-asserted, the transaction is in the final data phase or has completed. PCI Initiator Ready Pin Name: PCI_IRDY_N Pin Number: 105 Initiator Ready indicates the initializing agent's (bus master's) ability to complete the current data phase of the transaction. This signal is used with PCI_TRDY_N. A data phase is completed on any clock when both PCI_IRDY_N and PCI_TRDY_N are sampled as asserted. Wait cycles are inserted until both PCI_IRDY_N and PCI_TRDY_N are asserted together. PCI Target Ready Pin Name: PCI_TRDY_N Pin Number: 106 Target Ready indicates the target agent's ability to complete the current data phase of the transaction. PCI_TRDY_N is used with PCI_IRDY_N. A data phase is completed on any clock when both PCI_TRDY_N and PCI_IRDY_N are sampled asserted. During a read, PCI_TRDY_N indicates that valid data is present on PCI_AD[31:0]. During a write, it indicates the target is prepared to accept data. PCI Device Select Pin Name: PCI_DEVSEL_N Pin Number: 107 Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, PCI_DEVSEL_N indicates to a master whether any device on the bus has been selected. PCI Stop Pin Name: PCI_STOP_N Pin Number: 110 PCI_STOP_N indicates the current target is requesting that the master stop the current transaction. PCI Parity Error Pin Name: PCI_PERR_N Pin Number: 111 PCI_PERR_N indicates a data parity error between the current master and target on PCI. On a write transaction, the target always signals data parity errors back to the master on PCI_PERR_N. On a read transaction, the master asserts PCI_PERR_N to indicate to the system that an error was detected. PCI System Error Pin Name: PCI_SERR_N Pin Number: 112 System Error is for reporting address parity errors, data parity errors on Special Cycle Command, or any other system error where the result will be catastrophic. The PCI_SERR_N is a pure open drain and is actively driven for a single PCI clock by the agent reporting the error. The assertion of PCI_SERR_N is synchronous to the clock and meets the setup and hold times of all bused signals. However, the restoring of PCI_SERR_N to the de-asserted state is accomplished by a weak pull-up. Note that if an agent does not want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is required. PCI Parity Pin Name: PCI_PAR (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 28 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin Number: 113 PCI_PAR is even parity across PCI_AD[31:0] and PCI_CBE[3:0]_N. Parity generation is required by all PCI agents. PCI_PAR is stable and valid one clock after the address phase. For data phases PCI_PAR is stable and valid one clock after either PCI_IRDY_N is asserted on a write transaction or PCI_TRDY_N is asserted on a read transaction. Once PCI_PAR is valid, it remains valid until one clock after the completion of the current data phase. (PCI_PAR has the same timing as PCI_AD[31:0] but delayed by one clock.) PCI Request Pin Name: PCI_REQ_N Pin Number: 136 This signal indicates to the arbiter that this agent desires use of the PCI bus. PCI Grant Pin Name: PCI_GNT_N Pin Number: 137 This signal indicates to the agent that access to the PCI bus has been granted. In response to a PCI request, this is a point-topoint signal. Every master has its own PCI_GNT_N, which must be ignored while PCI_RST_N is asserted. PCI Interrupt A Pin Name: PCI_INTA_N Pin Number: 138 Interrupt A is used to request an interrupt on the PCI bus. PCI_INTA_N is open collector and is an open drain output. PCI Clock Signal Pin Names: PCI_CLK Pin Number: 140 Clock Signal provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals (except PCI_RST_N, and PCI_INTA_N) are sampled on the rising edge of PCI_CLK. All other timing parameters are defined with respect to this edge. PCI Reset Pin Name: PCI_RST_N Pin Number: 141 PCI_RST_N is an active low input that is used to set the internal registers to their initial state. PCI_RST_N is typically the system power-on reset signal as distributed on the PCI bus. 3.3.4 Miscellaneous I/O Ground Pin Name: VSS Pin Number: 1, 17, 27, 37, 52, 62, 73, 88, 99, 109, 119, 129 Ground reference point to power supply. PLL VDD Pin Name: PLL_VDD Pin Number: 2 Dedicated PLL Power supply (3.3 Volts +/- 10%). Refer to section 7.1 for PLL connections. PLL Charge Pump Bias Pin Name: PLL_CPBIAS Pin Number: 3 Dedicated PLL analog pin for charge pump bias. Refer to section 7.1 for PLL connections. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 29 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. PLL VCO Bias Pin Name: PLL_VCOBIAS Pin Number: 4 Dedicated PLL analog pin for VCO bias. Refer to section 7.1 for PLL connections. PLL Loop Filter Pin Name: PLL_LOOPFLT Pin Number: 5 Dedicated PLL analog input for off-chip loop filter. Refer to section 7.1 for PLL connections. PLL Ground Pin Name: PLL_GND Pin Number: 6 Dedicated PLL Ground (Power supply reference). Refer to section 7.1 for PLL connections. Test Mode Pin Name: TEST_MODE Pin Number: 7 This pin, in conjunction with other pins, enables various test functions within the device. This pin should tied to ground for normal operation. Power Supply Pin Name(s): VDD Pin Number(s): 16, 26, 36, 51, 61, 72, 87, 98, 108, 118, 128and144 Power Supply Input (3.3 volts +/- 10%) IDE Configuration Pin Names: JP Pin Numbers: 80 IDE Configuration Jumper Pin. JP Pin 0 1 CONFIGURATION RAID Class, PCI Class Code = 010400h IDE Class, PCI Class Code = 010185h Table 3-2: ATA Configuration This pin has an internal pull-up resistor, and if left unconnected, will default to `1'. Otherwise, tie this pin high (1,) or low (0) to select the desired mode. It is recommended that this pin to be tied to low (RAID Class) when Silicon Image drivers (RAID or Non-RAID) are used. Base Address 5 Enable Pin Name: BA5_EN Pin Number: 139 Base Address 5 Enable Jumper Pin. BA5_EN Pin 0 1 CONFIGURATION Base Address 5 Disabled ( Note 1) Base Address 5 Enabled (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 30 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Table 3-3: Base Address 5 Configuration Note 1: Reading Base Address 5 returns all zeroes. This pin does not have an internal resistor and therefore must be tied high (1) or low (0) to select the desired mode. It is recommended that this pin is enabled (tied high)() for all configurations. Internal Scan Enable Pin Name: SCAN_EN Pin Number: 142 This pin when active (high) will place all scan flip-flops into a scan mode. This pin should be tied to ground for normal operation. Memory Chip Select Pin Name: MEM_CS_N Pin Number: 143 This pin is used to select and enable the external memory. It is active low (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 31 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 4. Package Drawing 22.0 + 0.25 SQ 20.0 + 0.10 SQ 108 73 109 72 INDEX 144 37 PIN #1 0.50 NOM 0.22 + 0.05 36 Dimensions in millimeters 1.40 + 0.05 0.10 + 0.05 Figure 3-2: Package Drawing - 144 LQFP Part Ordering Number: SII0680ACLU144 (144pin LQFP lead free package) SII0680ACL144 (144pin LQFP standard package) (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 32 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Pin 1 designator location Logo SII0680ACL144 LLLLLL.LL YYWW SiI P/N Lot # (= Job#) Date Code Figure 3-3: Marking Specification - SII0680ACL144 Pin 1 designator location Logo SII0680ACLU144 LLLLLL.LL YYWW SiI P/N Lot # (= Job#) Date Code Figure 3-4: Marking Specification - SII0680ACLU144 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 33 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 5. ASIC Block Diagram The PCI-680 ASIC contains the major logic modules shown in Figure 5-1. PCI680 PCI680_CORE Bus Interface Data FIFO Parallel ATA Channel #0 PCI DMA Engine PCI Interface Flash & EEPROM Interface PCI DMA Engine Arbiter Bus Interface Data FIFO Parallel ATA Channel #1 400 MHz Phase Locked Loop Clock Select Figure 5-1: PCI-680 ASIC Block Diagram (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 34 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. PCI Bus PCI_AD[31:00] PCI_CBE[3:0] PCI_IDSEL PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_DEVSEL_N PCI_PAR PCI_PERR_N PCI_SERR_N PCI_REQ_N PCI_GNT_N PCI_M66EN PCI_CLK PCI_RST_N Bits 32 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Type I/O I/O I I/O I/O I/O I/O I/O I/O I/O OD T I I I I Description PCI address/data bus PCI command/byte enables PCI ID select PCI FRAME# signal PCI IRDY# signal PCI TRDY# signal PCI STOP# signal PCI DEVSEL# signal PCI parity bit PCI parity error signal PCI system error signal PCI bus request PCI bus grant PCI 66 MHz enable PCI clock PCI bus reset Table 5-1: PCI Bus Signals Group IDE Channel #0 IDE0_DD[15:00] IDE0_CS0_N IDE0_CS1_N IDE0_DA0 IDE0_DA1 IDE0_DA2 IDE0_DIOR_N IDE0_DIOW_N IDE0_DMACK_N IDE0_CBLID_N IDE0_INTRQ IDE0_IORDY IDE0_AT_REXT IDE0_DMARQ IDE0_RST_N Bits 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I I/O Description IDE data bus IDE chip select IDE chip select IDE device address IDE device address IDE device address IDE device IO read IDE device IO write IDE DMA acknowledge IDE cable ID IDE interrupt request IDE IO channel ready IDE external bias circuit IDE DMA request IDE reset Table 5-2: IDE Channel #0 Signals Group IDE Channel #1 IDE1_DD[15:00] IDE1_CS0_N IDE1_CS1_N IDE1_DA0 IDE1_DA1 IDE1_DA2 IDE1_DIOR_N IDE1_DIOW_N IDE1_DMACK_N IDE1_CBLID_N IDE1_INTRQ IDE1_IORDY IDE1_AT_REXT IDE1_DMARQ IDE1_RST_N Bits 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I I/O Description IDE data bus IDE chip select IDE chip select IDE device address IDE device address IDE device address IDE device IO read IDE device IO write IDE DMA acknowledge IDE cable ID IDE interrupt request IDE IO channel ready IDE external bias circuit IDE DMA request IDE reset Table 5-3: IDE Channel #1 Signals Group (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 35 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. FLASH Interface IDE0_DD[07] IDE0_DD[05] IDE0_DD[08] IDE0_DD[09] IDE0_DD[04] IDE0_DD[03] IDE0_DD[10] IDE0_DD[00] IDE0_DA2 IDE0_DD[01] IDE0_DD[02] IDE0_DD[11] IDE0_DD[12] IDE0_DD[13] IDE0_DD[14] IDE0_DD[15] IDE0_DA0 IDE0_CS0_N IDE0_CS1_N IDE1_DD[07] IDE1_DD[06] IDE1_DD[05] IDE1_DD[04] IDE1_DD[11] IDE1_DD[10] IDE1_DD[09] IDE1_DD[08] IDE0_DA1 IDE0_DD[06] MEM_CS_N Bits 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Type O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O O O O Description FLASH memory address bit 18 FLASH memory address bit 17 FLASH memory address bit 16 FLASH memory address bit 15 FLASH memory address bit 14 FLASH memory address bit 13 FLASH memory address bit 12 FLASH memory address bit 11 FLASH memory address bit 10 FLASH memory address bit 09 FLASH memory address bit 08 FLASH memory address bit 07 FLASH memory address bit 06 FLASH memory address bit 05 FLASH memory address bit 04 FLASH memory address bit 03 FLASH memory address bit 02 FLASH memory address bit 01 FLASH memory address bit 00 FLASH memory data bit 07 FLASH memory data bit 06 FLASH memory data bit 05 FLASH memory data bit 04 FLASH memory data bit 03 FLASH memory data bit 02 FLASH memory data bit 01 FLASH memory data bit 00 FLASH memory read strobe FLASH memory write strobe FLASH memory chip select Table 5-4: PCI-680 FLASH Memory Signals Group - Shared Signals EEPROM Interface IDE1_CS1_N IDE1_CS0_N Bits 1 1 Type O O Description EEPROM serial data EEPROM serial clock Table 5-5: PCI-680 EEPROM Memory Signals Group - Shared Signals Test Mode Signals SCAN_EN TEST_MODE Bits 1 1 Type I I Description ASIC internal scan mode enable ASIC test mode enable Table 5-6: PCI-680 Test Signals Group (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 36 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 6. Clocking System The SiI 0680A ASIC utilizes an on-chip 400 MHz PLL to synthesize the clock frequencies required to support the various ATA modes. The clock frequency for the ATA UDMA mode logic is software programmable for 66, 100 or 133 MHz. The ATA clock can also be disabled. The clock frequency for the PCI interface logic and most of the device is derived from the 33 MHz PCI bus clock. The clock tree for ATA Channel #1 is offset by 5 nsec relative to the clock tree for IDE Channel #0. This reduces the amount of simultaneous switching activity within the core and on external pins. Several test modes within the clocking system are required for PLL and internal scan testing. These topics are covered in Chapter 10. JP Test Register SYS_NAND_TEST Nand Tree Normal Function 1 PCI_INTA_N 0 Normal Function 0 RST_PLL_TEST 4K & 1 MEM_CS_N PCI_IDSEL & SCAN_MODE BA5_EN & 1 PLL_TEST_CLK_SEL 33 MHz P_CLK 0 & 2 SYS_IDE_CLKSEL[1:0] PLL_TEST_MODE 2 3 TEST_MODE PCI_GNT_N ( FB Clock ) (Ref Clock) & 3 PLL 0 133 MHz 2 1 0 0 1 I0_CLK 100 MHz PCI_CLK (Test Clock) IDE0_DMARQ 2 2 5ns 0 1 I1_CLK 1 2 (Test Clock) PCI_CLK x 2 IDE0_CBLID_N IDE1_CBLID_N SCAN_EN (Test Clock) To all scan flip flops Figure 6-1: SiI 0680A Clocking System and Test Feature Diagram (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 37 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 7. Phased Locked Loop (PLL) 7.1 PLL Connections The SiI 0680A ASIC utilizes an on-chip Phase Locked Loop (PLL) for high frequency clock synthesis. The PLL is designed to generate a 400 MHz internal clock, which is divided down to produce the clocks for the ATA UDMA interface logic, and is further divided down to produce 33 MHz for the system logic. 7.1.1 PLL Schematic The schematic of PLL related components are shown in Figure 7-1. Reference Designators shown are for illustration purposes only and do not reflect those on the evaluation board. The values are subject to change. Please contact Silicon Image for the latest revision of the schematic for current reference designators and component values used on evaluation boards. Figure 7-1: Schematic of PLL Circuitry (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 38 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 7.1.2 PLL Components Recommended part specifications: 1.) Ferrite Bead = 40 Ohm, 300ma, 0805 Qty = 1 Ref Des. = L1 Example Part Numbers: ACT DCB-0805 Steward-USA LI0805E400R AEM MCB0805F400 2.) Resistor = Metal Film, 10.5K Ohm, 1%, 1/10W, 0805 Qty = 1 Ref Des. = R3 Example Part Numbers: Rohm - MCR10-EZHM-F-1052 KOA - RM73-B-2A-T-1052-F Meritek - CR10-1052-F Dale - CRCW0805-1052FT 3.) Resistor = Metal Film, 10.0K Ohm, 1%, 1/10W, 0805 Qty = 1 Ref Des. = R2 Example Part Numbers: Rohm - MCR10-EZHM-F-1002 KOA - RM73-B-2A-T-1002-F Meritek - CR10-1002-F Dale - CRCW0805-1002FT 4.) Resistor = Metal Film, 2.0K Ohm, 1%, 1/10W, 0805 Qty = 1 Ref Des. = R1 Example Part Numbers: Rohm - MCR10-EZHM-F-2001 KOA - RM73-B-2A-T-2001-F Meritek - CR10-2001-F Dale - CRCW0805-2001FT 5.) Capacitor = Ceramic, 6.8pF, 50V, 5%, NPO, 0805 Qty = 1 Ref Des. = C4 Example Part Numbers: AVX - 0805-5-A-689-J Rohm - MCH21-5A-6R8-JK Johanson - 101-R15-N-6R8-J-V4E Kemet - C0805C689J5GAC 6.) Capacitor = Ceramic, 220pF, 50V, 5%, NPO, 0805 Qty = 1 Ref Des. = C5 Example Part Numbers: AVX - 0805-5-A-221-J Rohm - MCH21-5A-221-JK Johanson - 101-R15-N-221-J-V4E Kemet - C0805C221J5GAC 7.) Capacitor = Ceramic, 0.01uF, 50V, 20%, Y5V, 0805 Qty = 2 Ref Des. = C1, C3 Example Part Numbers: AVX - 0805-5-G-103-M Rohm - MCH21-5-C-103-KK Johanson - 500-R15-Z-103-M-V6E Kemet - C0805C103M5UAC 8.) Capacitor = Ceramic, 0.1uF, 50V, 20%, X7R, 0805 Qty = 1 Ref Des. = C2 Example Part Numbers: AVX - 0805-5-C-104-KATMA Rohm - MCH21-5-E-104-M Johanson - 500-R15-W-104-M-V4E (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 39 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Kemet - C0805C104M5UAC 7.1.3 PLL Layout Requirements The SiI 0680A uses a high speed Phase Lock Loop (PLL) for clock generation. The layout of this high-speed analog circuit is critical to the proper operation of the circuit. Power and Ground Planes should be used with the Ground Plane located directly under the top external layer. Isolated "islands" for power and ground plane should be used to isolate high-speed digital currents from the PLL circuitry. The isolated planes should be identical in size and shape. Figures 7-2 and 7-3 show an example 4-layer layout. The SiI 0680A's pin PLL_VDD (pin 2) should be connected to the isolated PLL_VDD plane. This plane should be completely isolated with no connection to the main power plane. The SiI 0680A's pin PLL_GND (pin 6) should be connected to the isolated PLL_GND plane. The "island" should be connected to the ground plane with a narrow "bridge" of at least 0.015" width of copper. Locate this "bridge" directly under L1 as shown in Figure 7-2. The PLL components (C2, C3, C4, C5, R1, R2, and R3) should be mounted on top of the PLL_GND "island". The island should cover all areas under the components, their pads and connected traces. No PLL circuitry should be exposed (be located on top of) to either the main ground plane or cut in the planes. Only the listed PLL components should connect to the "island". No other ground connections should be made there. It is important to keep the trace lengths short. No high-speed digital signals should be allowed to pass through, above or below, any portion of the power and ground "islands". Take extra care to make sure the data bits located on pins 8 through 15 are routed clear of the "islands". (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 40 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Figure 7-2: Example Layout - Ground Plane (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 41 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Figure 7-2: Example Layout - Power Plane (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 42 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 8. Auto-Initialization The SiI 0680A ASIC supports an external FLASH and/or EEPROM device for BIOS extensions and user-defined PCI configuration header data. Interface to either memory device is performed through a set of special function ATA pins. These pins are active in the SiI 0680A auto-initialization mode after release of PCI_RST_N, and return to normal ATA function mode after the auto-initialization is complete. 8.1 Auto-Initialization from FLASH The SiI 0680A initiates the FLASH detection and configuration space loading sequence upon the release of PCI_RST_N. It begins by reading the highest two addresses (7FFFFH and 7FFFEH), checking for the correct data signature pattern - AAH and 55H, respectively. If the data signature pattern is correct, the SiI 0680A continues to sequence the address downward, reading a total of twelve bytes. If the Data Signature is correct (55H at 7FFFCH), the last eight bytes are loaded into the PCI Configuration Space registers. Note: If both Flash and EEPROM are installed, the PCI Configuration Space registers will be loaded with EEPROM's data. While the sequence is active, the SiI 0680A responds to all PCI bus accesses with a Target Retry. MEM_ADDR MEM_DATA MEM_RD_N MEM_WR_N t1 MEM_CS_N PCI_RST_N Figure 8-1: Auto-Initialization from Flash Timing t2 7FFFF 7FFFE 7FFFD 7FFFC 7FFFB 7FFFA 7FFF9 7FFF8 7FFF7 7FFF6 7FFF5 7FFF4 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 Parameter t1 t2 Value 660 ns 7200 ns Description PCI reset to Flash Auto-Initialization cycle begin Flash Auto-Initialization cycle time Table 8-1: Auto-Initialization from Flash Timing (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 43 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Address 7FFFFH 7FFFEH 7FFFDH 7FFFCH 7FFFBH 7FFFAH 7FFF9H 7FFF8H 7FFF7H 7FFF6H 7FFF5H 7FFF4H Data Byte D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 Data Signature = AAH Data Signature = 55H Description AA = 120 ns FLASH device / Else, 240 ns FLASH device Data Signature = 55H PCI Device ID [23:16] PCI Device ID [31:24] PCI Class Code [15:08] PCI Class Code [23:16] PCI Sub-System Vendor ID [07:00] PCI Sub-System Vendor ID [15:08] PCI Sub-System ID [23:16] PCI Sub-System ID [31:24] Table 8-2: FLASH Data Description 8.2 Auto-Initialization from EEPROM The SiI 0680A initiates the EEPROM detection and configuration space loading sequence after the FLASH read sequence. The SiI 0680A supports up to 256 byte EEPROM with a 2-wire serial interface. The sequence of operations consists of the following. 1) START condition defined as a high-to-low transition on SDAT while SCLK is high. 2) Control byte = 1010 (Control Code) + 000 (Chip Select) + 0 (Write Address) 3) Acknowledge 4) Starting address field = 00000000. 5) Acknowledge 6) Sequential data bytes separated by Acknowledges. 7) STOP condition. While the sequence is active, the SiI 0680A responds to all PCI bus accesses with a Target Retry. S SDAT t1 SCLK t3 MEM_CS_N Figure 8-2: Auto-Initialization from EEPROM Timing t2 1 0 1 0 0 0 0 W A D D D N P (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 44 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Parameter t1 t2 t3 Value 26.00 s 2.66 ms 19.26 s Description End of Auto-Initialization from FLASH to start of Auto-Initialization from EEPROM Auto-Initialization from EEPROM cycle time EEPROM serial clock period Table 8-3: Auto-Initialization from EEPROM Timing Parameter S W A D N P START condition Description R/W 0 = Write Command, 1 = Read Command Acknowledge Serial data No-Acknowledge STOP condition Table 8-4: Auto-Initialization from EEPROM Timing Symbols Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Data Byte D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D0A D0B Description Memory Present Pattern = AAH Memory Present Pattern = 55H Data Signature = AAH Data Signature = 55H PCI Device ID [23:16] PCI Device ID [31:24] PCI Class Code [15:08] PCI Class Code [23:16] PCI Sub-System Vendor ID [07:00] PCI Sub-System Vendor ID [15:08] PCI Sub-System ID [23:16] PCI Sub-System ID [31:24] Table 8-5: EEPROM Data Description (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 45 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9. Register Definitions This section describes the registers within the SiI 0680A PCI-ATA host controller ASIC. 9.1 PCI Configuration Space The PCI Configuration Space registers define the operation of the SiI 0680A on the PCI bus. These registers are accessible only when the SiI 0680A detects a Configuration Read or Write operation, with its IDSEL asserted, on the 32-bit PCI bus. Table 9-1, outlines the PCI Configuration space for the SiI 0680A. Address Offset Register Name 31 16 Device ID (0680h) PCI Status PCI Class Code BIST Header Type Latency Timer 15 00 Vendor ID (1095h) PCI Command Revision ID Cache Line Size Access Type 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Base Address Register 0 Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 Base Address Register 5 Reserved Subsystem ID (0680h) Subsystem Vendor ID (1095h) R/W R/W Expansion ROM Base Address Reserved Reserved Max Latency Min Grant Reserved Software Data Register Reserved Reserved Reserved Interrupt Pin Interrupt Line Configuration Capabilities Ptr R R/W R/W R/W R/W - Table 9-1: PCI-680 PCI Configuration Space (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 46 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Address Offset Register Name 31 16 Reserved Reserved Reserved Power Management Capabilities Data Reserved Reserved Reserved Reserved PCI Bus Master Status - IDE0 Reserved PCI Bus Master Command - IDE0 Next Item Pointer Capability ID 15 00 Access Type 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H 84H 88H 8CH 90H 94H 98H 9CH A0H A4H A8H ACH B0H B4H B8H BCH Reserved R/W R/W R/W R/W PCI Bus Master Command - IDE1 R/W R/W IDE0 Data Transfer Mode IDE1 Data Transfer Mode System Command R/W R/W R/W R/W R/W Flash Memory Data R/W R/W R/W R/W R/W R/W R/W Cmd + Status R/W R/W R/W R/W Functions Control and Status PRD Table Address - IDE0 PCI Bus Master Status - IDE1 Reserved PRD Table Address - IDE1 Reserved Reserved System Configuration Status System Software Data FLASH Memory Address - Command + Status Reserved EEPROM Memory Address - Command + Status Reserved IDE0 TF Timing IDE0 Device 1 PIO Timing IDE0 Device 1 DMA Timing IDE0 Device 1 UDMA Timing IDE1 TF Timing IDE1 Device 1 PIO Timing IDE1 Device 1 DMA Timing IDE1 Device 1 UDMA Timing IDE1 IDE0 Config + Status EEPROM Memory Data IDE0 + Status Cmd IDE0 Device 0 PIO Timing IDE0 Device 0 DMA Timing IDE0 Device 0 UDMA Timing Config + Status IDE1 IDE1 Device 0 PIO Timing IDE1 Device 0 DMA Timing IDE1 Device 0 UDMA Timing Table 9-1: SiI 0680A PCI Configuration Space (continued) (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 47 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.1 Device ID - Vendor ID Address Offset: 00H Access Type: Read /Write Reset Value: 0x0680_1095 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device ID Vendor ID This register defines the Device ID and Vendor ID associated with the SiI 0680A. The register bits are defined below. * Bit [31:16]: Device ID (R/W) - Device ID. This value in this bit field is determined by any one of three options: * 1) This field defaults to 0x0680 to identify the device as a Silicon Image SiI 0680A. * 2) loaded from an external memory device : If an external memory device - FLASH or EEPROM - is present with the correct signature, the PCI Class Code is loaded from that device after reset. The correct signature for an EEPROM device is the data pattern 55AAH at addresses [03H:02H] and 55AAH at addresses [01H:00H]. The correct signature for a FLASH device is the data pattern AA55H at addresses [7FFFFH:7FFFEH] and 55H at address 7FFFCH. See chapter 8 for details. * 3) system programmable : If Bit 0 of the Configuration register (40H) is set, to enables writes, the three bytes are system programmable. Bit [15:00]: Vendor ID (R) - Vendor ID. This field defaults to 0x1095 to identify the vendor as Silicon Image/CMD Technology. * 9.1.2 PCI Status - PCI Command Address Offset: 04H Access Type: Read/Write/Write-One-to-Clear Reset Value: 0x0290_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Det M Data Par Err Address Stepping Memory Wr & Inv Capabilities List 66 MHz Capable SERR Enable Rcvd T Abort VGA Palette Bus Master Fast B-to-B Sig T Abort Fast B-to-B Sig Sys Err Det Par Err Reserved Memory Space Special Cycles Devsel Timing Rcvd M Abort Reserved Par Error IO Space This register defines the various control functions associated with the PCI bus. The register bits are defined below. * * * * * * * * * Bit 31: Det. Par Err (R/W1C) - Detected Parity Error. This bit set indicates that the SiI 0680A detected a parity error on the PCI bus-address or data parity error-while responding as a PCI target. Bit 30: Sig. Sys Err (R/W1C) - Signaled System Error. This bit set indicates that the SiI 0680A signaled SERR on the PCI bus. Bit 29: Rcvd M Abort (R/W1C) - Received Master Abort. This bit set indicates that the SiI 0680A terminated a PCI bus operation with a Master Abort. Bit 28: Rcvd T Abort (R/W1C) - Received Target Abort. This bit set indicates that the SiI 0680A received a Target Abort termination. Bit 27: Sig. T Abort (R/W1C) - Signaled Target Abort. This bit set indicates that the SiI 0680A terminated a PCI bus operation with a Target Abort. Bit [26:25]: Devsel Timing (R) - Device Select Timing. This bit field indicates the DEVSEL timing supported by the SiI 0680A. The hardwired value is 01B for Medium decode timing. Bit 24: Det M Data Par Err (R/W1C) - Detected Master Data Parity Error. This bit set indicates that the SiI 0680A, as bus master, detected a parity error on the PCI bus. The parity error may be either reported by the target device via PERR# on a write operation or by the SiI 0680A on a read operation. Bit 23: Fast B-to-B Capable (R) - Fast Back-to-Back Capable. This bit is hardwired to 1 to indicate that the SiI 0680A is Fast Back-to-Back capable as a PCI target. Bit 22: Reserved (R). (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 48 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. * * * * * * * * * * * * * Bit 21: 66 MHz Capable (R) - 66 MHz PCI Operation Capable. This bit is hardwired to 0 to indicate that the SiI 0680A is not 66 MHz capable. Bit 20: Capabilities List (R) - PCI Capabilities List. This bit is hardwired to 1 to indicate that the SiI 0680A has a PCI Power Management Capabilities register linked at offset 34H. Bit [19:10]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit 09: Fast B-to-B Enable (R) - Fast Back-to-Back Enable. This bit is hardwired to 0 to indicate that the SiI 0680A does not support Fast Back-to-Back operations as bus master. Bit 08: SERR Enable (R/W) - SERR Output Enable. This bit set enables the SiI 0680A to drive the PCI SERR# pin when it detects an address parity error. The Parity Error Response bit (06) must also be set to enable SERR# reporting. Bit 07: Address Stepping (R) - Address Stepping Enable. This bit is hardwired to 0 to indicate that the SiI 0680A does not support Address Stepping. Bit 06: Par Error Response (R/W) - Parity Error Response Enable. This bit set enables the SiI 0680A to respond to parity errors on the PCI bus. If this bit is cleared, the SiI 0680A will ignore PCI parity errors. Bit 05: VGA Palette (R) - VGA Palette Snoop Enable. This bit is hardwired to 0 to indicate that the SiI 0680A does not support VGA Palette Snooping. Bit 04: Mem Wr & Inv (R) - Memory Write and Invalidate Enable. This bit is hardwired to 0 to indicate that the SiI 0680A does not support Memory Write and Invalidate. Bit 03: Special Cycles (R) - Special Cycles Enable. This bit is hardwired to 0 to indicate that the SiI 0680A does not respond to Special Cycles. Bit 02: Bus Master (R/W) - Bus Master Enable. This bit set enables the SiI 0680A to act as PCI bus master. Bit 01: Memory Space (R/W) - Memory Space Enable. This bit set enables the SiI 0680A to respond to PCI memory space access. Bit 00: IO Space (R/W) - IO Space Enable. This bit set enables the SiI 0680A to respond to PCI IO space access. 9.1.3 PCI Class Code - Revision ID Address Offset: 08H Access Type: Read/Write Reset Value: 0x0101_8501 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Pwr-Up Mode PCI Class Code PCI Prog Int IDE0 Pwr-Up Mode IDE1 Mode Prog IDE0 Mode Prog Revision ID This register defines the various control functions associated with the PCI bus. The register bits are defined below. * Bit [31:08]: PCI Class Code (R) - PCI Class Code. This value in this bit field is determined by any one of three options: * 1) the default value, set by an external jumper: If JP = 0, the value is 010400h for RAID mode If JP = 1, the value is 010185h for ATA mode * 2) loaded from an external memory device : If an external memory device - FLASH or EEPROM - is present with the correct signature, the PCI Class Code is loaded from that device after reset. The correct signature for an EEPROM device is the data pattern 55AAH at addresses [03H:02H] and 55AAH at addresses [01H:00H]. The correct signature for a FLASH device is the data pattern AA55H at addresses [7FFFFH:7FFFEH] and 55H at address 7FFFCH. See chapter 8 for details. * 3) system programmable : If Bit 0 of the Configuration register (40H) is set, to enables writes, the three bytes are system programmable. Bit [07:00]: Revision ID (R) - Chip Revision ID. This bit field is hardwired to 01H to indicate the first revision silicon. * (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 49 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.4 BIST - Header Type - Latency Timer - Cache Line Size Address Offset: 0CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 BIST Header Type Latency Timer Cache Line Size This register defines the various control functions associated with the PCI bus. The register bits are defined below. * * * * Bit [31:24]: BIST (R). This bit field is hardwired to 00H. Bit [23:16]: Header Type (R). This bit field is hardwired to 00H. Bit [15:08]: Latency Timer (R/W). This bit field is used to specify the time in number of PCI clocks, the SiI 0680A as a master is still allowed to control the PCI bus after its GRANT_L is deasserted. The lower four bits [0B:08] are hardwired to 0 H , resulting in a time granularity of 16 clocks. Bit [07:00]: Cache Line Size (R/W). This bit field is used to specify the system cacheline size in terms of 32-bit words. The upper 2 bits are not used, resulting a maximum size of 64 32-bit words. With the SiI 0680A as a master, initiating a read transaction, it issues PCI command Read Multiple in place , when empty space in its FIFO is larger than the value programmed in this register. 9.1.5 Base Address Register 0 Address Offset: 10H Access Type: Read/Write Reset Value: 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 0 Not Used This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below. * * Bit [31:03]: Base Address Register 0 (R/W). This register defines the I/O Space base address for the IDE Channel #0 task file registers. Bit [02:00]: Base Address Register 0 (R). This bit field is not used and is hardwired to 001B 9.1.6 Base Address Register 1 Address Offset: 14H Access Type: Read/Write Reset Value: 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 1 Not Used This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below. * * Bit [31:02]: Base Address Register 1 (R/W). This register defines the I/O Space base address for the IDE Channel #0 Device Control- Alternate Status register. Bit [01:00]: Base Address Register 1 (R). This bit field is not used and is hardwired to 01B. SiI-DS-0069-C 50 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.7 Base Address Register 2 Address Offset: 18H Access Type: Read/Write Reset Value: 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 2 Not Used This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below. * * Bit [31:03]: Base Address Register 2 (R/W). This register defines the I/O Space base address for the IDE Channel #1 task file registers. Bit [02:00]: Base Address Register 2 (R). This bit field is not used and is hardwired to 001B. 9.1.8 Base Address Register 3 Address Offset: 1CH Access Type: Read/Write Reset Value: 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 3 Not Used This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below. * * Bit [31:02]: Base Address Register 3 (R/W). This register defines the I/O Space base address for the IDE Channel #1 Device Control- Alternate Status register. Bit [01:00]: Base Address Register 3 (R). This bit field is not used and is hardwired to 01B. 9.1.9 Base Address Register 4 Address Offset: 20H Access Type: Read/Write Reset Value: 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 4 Not Used This register defines the addressing of various control functions within the SiI 0680A. The register bits are defined below. * * Bit [31:04]: Base Address Register 4 (R/W). This register defines the I/O Space base address for the PCI bus master registers. Bit [03:00]: Base Address Register 4 (R). This bit field is not used and is hardwired to 0001B. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 51 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.10 Base Address Register 5 Address Offset: 24H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Base Address Register 5 Not Used This register defines the addressing of various control functions within the SiI 0680A. This register is enabled when input BA5_EN is set to one. See section 3.1.5 for descriptions. The register bits are defined below. * * Bit [31:08]: Base Address Register 5 (R/W). This register defines the Memory Space base address for all Silicon Image driver specific functions. Bit [07:00]: Base Address Register 5 (R). This bit field is not used and is hardwired to 00H. 9.1.11 Subsystem ID - Subsystem Vendor ID Address Offset: 2CH Access Type: Read/Write Reset Value: 0x0680_1095 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Subsystem ID Subsystem Vendor ID This register defines the Subsystem ID fields associated with the PCI bus. See chapter 8 for details. The register bits are defined below. * * Bit [31:16]: Subsystem ID (R) - Subsystem ID. Bit [15:00]: Subsystem Vendor ID (R) - Subsystem Vendor ID. The value in this bit field is determined by any one of three options: * 1) Bit [31:16]: Subsystem ID (R) - Subsystem ID defaults to 0680AH. Bit [15:00]: Subsystem Vendor ID (R) - Subsystem Vendor ID defaults to 1095H. * 2) loaded from an external memory device : If an external memory device - FLASH or EEPROM - is present with the correct signature, the PCI Class Code is loaded from that device after reset. The correct signature for an EEPROM device is the data pattern 55AAH at addresses [03H:02H] and 55AAH at addresses [01H:00H]. The correct signature for a FLASH device is the data pattern AA55H at addresses [7FFFFH:7FFFEH] and 55H at address 7FFFCH. See chapter 8 for details. * 3) system programmable : If Bit 0 of the Configuration register (40H) is set, to enables writes, the three bytes are system programmable. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 52 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.12 Expansion ROM Base Address Address Offset: 30H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Expansion ROM Base Address Not Used Exp ROM Enable Capabilities Pointer Interrupt Line This register defines the Expansion ROM base address associated with the PCI bus. The register bits are defined below. * * * Bit [31:19]: Expansion ROM Base Address (R/W) - Expansion ROM Base Address. This bit field defines the upper bits of the Expansion ROM base address. Bit [18:01]: Not Used (R). This bit field is hardwired to 00000H. The minimum Expansion ROM address range is 512K bytes. Bit [00]: Exp ROM Enable (R/W) - Expansion ROM Enable. This bit is set to enable the Expansion ROM access. 9.1.13 Capabilities Pointer Address Offset: 34H Access Type: Read Reset Value: 0x0000_0060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved This register defines the link to a list of new capabilities associated with the PCI bus. The register bits are defined below. * * Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [07:00]: Capabilities Pointer (R) - Capabilities Pointer. This bit field defaults to 60H to define the address for the 1st entry in a list of PCI Power Management capabilities. 9.1.14 Max Latency - Min Grant - Interrupt Pin - Interrupt Line Address Offset: 3CH Access Type: Read/Write Reset Value: 0x0000_0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Max Latency Min Grant Interrupt Pin This register defines the various control functions associated with the PCI bus. The register bits are defined below. * * * * Bit [31:24]: Max Latency (R) - Maximum Latency. This bit field is hardwired to 00H. Bit [23:16]: Min Grant (R) - Minimum Grant. This bit field is hardwired to 00H. Bit [15:08]: Interrupt Pin (R) - Interrupt Pin Used. This bit field is hardwired to 01H to indicate that the SiI 0680A uses the INTA# interrupt. Bit [07:00]: Interrupt Line (R/W) - Interrupt Line. This bit field is used by the system to indicate interrupt line routing information. The SiI 0680A does not use this information. SiI-DS-0069-C 53 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.15 Configuration Address Offset: 40H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved PCI Hdr Wr Ena Next Item Pointer Capability ID This register defines the various control functions associated with the PCI bus. The register bits are defined below. * * Bit [31:01]: Reserved (R). This bit field is hardwired to 00000000H. Bit [00]: PCI Hdr Wr Ena (R/W) - PCI Configuration Header Write Enable. This bit is set to enable write access to the following registers in the PCI Configuration Header: Device ID (03-02H), PCI Class Code (09-0BH), Subsystem Vendor ID (2D-2CH), and Subsystem ID (2F-2EH). 9.1.16 Software Data Register Address Offset: 44H Access Type: Read/Write Reset Value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Software Data This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are never cleared by any type of reset. 9.1.17 Power Management Capabilities Address Offset: 60H Access Type: Read Only Reset Value: 0x0622_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PPM D2 Support PPM D1 Support PME Clock PME Support Reserved Auxiliary Current Dev Special Init PPM Rev This register defines the power management capabilities associated with the PCI bus. The register bits are defined below. * * * * * * Bit [31:27]: PME Support (R) - Power Management Event Support. This bit field is hardwired to 00H to indicate that the SiI 0680A does not support PME. Bit [26]: PPM D2 Support (R) - PCI Power Management D2 Support. This bit is hardwired to 1 to indicate support for the D2 Power Management State. Bit [25]: PPM D1 Support (R) - PCI Power Management D1 Support. This bit is hardwired to 1 to indicate support for the D1 Power Management State. Bit [24:22]: Auxiliary Current (R) - Auxiliary Current. This bit field is hardwired to 000B. Bit [21]: Dev Special Init (R) - Device Special Initialization. This bit is hardwired to 1 to indicate that the SiI 0680A does not require special initialization Bit [20]: Reserved (R). This bit is reserved and returns zero on a read. SiI-DS-0069-C 54 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. * * * * Bit [19]: PME Clock (R) - Power Management Event Clock. This bit is hardwired to 0. The SiI 0680A does not support PME. Bit [18:16]: PPM Rev (R) - PCI Power Management Revision. This bit field is hardwired to 010B to indicate compliance with the PCI Power Management Interface Specification revision 1.1. Bit [15:08]: Next Item Pointer (R) - PCI Additional Capability Next Item Pointer. This bit field is hardwired to 00H to indicate that there are no additional items on the Capabilities List. Bit [07:00]: Capability ID (R) - PCI Additional Capability ID. This bit field is hardwired to 01H to indicate that this Capabilities List is a PCI Power Management definition. 9.1.18 Power Management Control + Status Address Offset: 64H Access Type: Read/Write Reset Value: 0x6400_4000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PME Status PPM Data Reserved PPM Data Sel PME Ena Reserved PPM Power State PPM Data Scale This register defines the power management capabilities associated with the PCI bus. The register bits are defined below. * * * * * * * * Bit [31:24]: PPM Data (R) - PCI Power Management Data. This bit field is hardwired to 64h. Bit [23:16]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [15]: PME Status (R) - PME Status. This bit field is hardwired to 0. The SiI 0680A does not support PME. Bit [14:13]: PPM Data Scale (R) - PCI Power Management Data Scale. This bit field is hardwired to 11B to indicate a scaling factor of one. Bit [12:09]: PPM Data Sel (R/W) - PCI Power Management Data Select. This bit field is set by the system to indicate which data field is to be reported through the PPM Data bits. Bit [08]: PME Ena (R) - PME Enable. This bit field is hardwired to 0. The SiI 0680A does not support PME. Bit [07:02]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [01:00]: PPM Power State (R/W) - PCI Power Management Power State. This bit field is set by the system to dictate the current Power State: 00 = D0 (Normal Operation), 01 = D1, 10 = D2, and 11 = D3 Hot. 9.1.19 PCI Bus Master - IDE0 Address Offset: 70H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PBM Simplex PBM Enable PBM Active PBM Rd-Wr PBM Error Reserved IDE0 DMA Comp PBM DMA Cap 1 PBM DMA Cap 0 Reserved Reserved Reserved Reserved This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 4, Offset 00H, Base Address 5, Offset 00H, and Base Address 5, Offset 10H. See Section 9.7.1 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 55 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.20 PRD Table Address - IDE0 Address Offset: 74H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Table Address - IDE0 Reserved This register defines the PRD Table Address register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 4, Offset 04H and Base Address 5, Offset 04H. See Section 9.7.2 for bit definitions. 9.1.21 PCI Bus Master - IDE1 Address Offset: 78H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PBM Simplex PBM Enable PBM Active PBM Rd-Wr PBM Error Reserved IDE1 DMA Comp PBM DMA Cap 1 PBM DMA Cap 0 Reserved Reserved Reserved Reserved Reserved This register defines the PCI bus master register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 4, Offset 08H, Base Address 5, Offset 08H, and Base Address 5, Offset 18H. See Section 9.7.3 for bit definitions. 9.1.22 PRD Table Address - IDE1 Address Offset: 7CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Table Address - IDE1 This register defines the PRD Table Address register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 4, Offset 0CH and Base Address 5, Offset 0CH. See Section 9.7.4 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 56 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.23 Data Transfer Mode - IDE0 Address Offset: 80H Access Type: Read/Write Reset Value: 0x0000_0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Device 1 Transfer Mode Reserved Reserved IDE0 Device 0 Transfer Mode Reserved This register defines the transfer mode register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset B4H. See Section 9.7.38 for bit definitions. 9.1.24 Data Transfer Mode - IDE1 Address Offset: 84H Access Type: Read/Write Reset Value: 0x0000_0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Device 1 Transfer Mode Reserved Reserved IDE1 Device 0 Transfer Mode Reserved This register defines the transfer mode register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset F4H. See Section 9.7.52 for bit definitions. 9.1.25 System Configuration Status - Command Address Offset: 88H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Module Rst FF0 Module Rst FF1 Module Rst IDE1 Int Block IDE0 Int Block IDE Clk Select Reserved BA5_EN PBM Module Rst ARB Module Rst Reserved Reserved IDE1 Module Rst Reserved This register defines the system configuration status and command register for the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 48H. See Section 9.7.13 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 57 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.26 System Software Data Register Address Offset: 8CH Access Type: Read/Write Reset Value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 System Software Data This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are never cleared by any type of reset. The register bits are also mapped to Base Address 5, Offset 4CH. See Section 9.7.14 for bit definitions. 9.1.27 FLASH Memory Address - Command + Status Address Offset: 90H Access Type: Read/Write Reset Value: 0x0000_0000 This register defines the address and command/status register for FLASH memory interface in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 50H. See Section 9.7.15 for bit definitions. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Mem Access Type Mem Access Start Mem Init Done Reserved Memory Address Reserved 9.1.28 FLASH Memory Data Address Offset: 94H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Memory Data This register defines the data register for FLASH memory interface in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 54H. See Section 9.7.16 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 58 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.29 EEPROM Memory Address - Command + Status Address Offset: 98H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mem Error Reserved Mem Access Type Mem Access Start Mem Init Done Reserved Mem Address Reserved This register defines the address and command/status register for EEPROM memory interface in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 58H. See Section 9.7.17 for bit definitions. 9.1.30 EEPROM Memory Data Address Offset: 9CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Memory Data This register defines the data register for EEPROM memory interface in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 5CH. See Section 9.7.18 for bit definitions. 9.1.31 IDE0 Task File Timing + Configuration + Status Address Offset: A0H Access Type: Read/Write Reset Value: 0x6515_0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Watchdog Timeout IORDY Monitoring Watchdog Int Ena Buffered Cmd Channel Rst Reserved Reserved Cable 80 Addr Setup Count Active Count Recovery Count Reserved Channel Tri-State Interrupt Status Virtual DMA Int Watchdog Ena This register defines the task file timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset A0H. See Section 9.7.33 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 59 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.32 IDE0 PIO Timing Address Offset: A4H Access Type: Read/Write Reset Value: 0x62DD_62DD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the PIO timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset A4H. See Section 9.7.34 for bit definitions. 9.1.33 IDE0 DMA Timing Address Offset: A8H Access Type: Read/Write Reset Value: 0x4392_4392 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the DMA timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset A8H. See Section 9.7.35 for bit definitions. 9.1.34 IDE0 UDMA Timing Address Offset: ACH Access Type: Read/Write Reset Value: 0x4009_4009 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Data Input Delay Device 0 Data Input Delay Device 1 DSTROBE Delay Device 1 HSTROBE Delay Device 0 DSTROBE Delay Reserved Reserved Device 1 Cycle Time Count Device 0 HSTROBE Delay Device 0 Cycle Time Count This register defines the UDMA timing register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset ACH. See Section 9.7.36 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 60 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.35 IDE1 Task File Timing + Configuration + Status Address Offset: B0H Access Type: Read/Write Reset Value: 0x6515_0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Watchdog Timeout IORDY Monitoring Watchdog Int Ena Interrupt Status Virtual DMA Int Watchdog Ena Buffered Cmd Channel Rst Reserved Addr Setup Count Active Count Recovery Count Reserved Channel Tri-State This register defines the task file timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset E0H. See Section 9.7.47 for bit definitions. 9.1.36 IDE1 PIO Timing Address Offset: B4H Access Type: Read/Write Reset Value: 0x62DD_62DD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the PIO timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset E4H. See Section 9.7.48 for bit definitions. 9.1.37 IDE1 DMA Timing Address Offset: B8H Access Type: Read/Write Reset Value: 0x4392_4392 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the DMA timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset E8H. See Section 9.7.48 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 61 Cable 80 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.1.38 IDE1 UDMA Timing Address Offset: BCH Access Type: Read/Write Reset Value: 0x4009_4009 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Data Input Delay Device 0 Data Input Delay Device 1 DSTROBE Delay Device 1 HSTROBE Delay Device 0 DSTROBE Delay Reserved Reserved Device 1 Cycle Time Count Device 0 HSTROBE Delay Device 0 Cycle Time Count This register defines the UDMA timing register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset ECH. See Section 9.7.50 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 62 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.2 Internal Register Space - Base Address 0 These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space. Address Offset Register Name 31 16 IDE0 TF Starting Sector Number IDE0 TF Command+Status IDE0 TF Sector Count IDE0 TF Device+Head IDE0 TF Features IDE0 TF Error IDE0 TF Cylinder High 15 00 IDE0 TF Data IDE0 TF Cylinder Low Access Type 00H 04H R/W R/W Table 9-2: SiI 0680A Internal Register Space - Base Address 0 9.2.1 IDE0 Task File Register 0 Address Offset: 00H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Task File Starting Sector Number IDE0 Task File Sector Count IDE0 Task File Features (W) IDE0 Task File Error (R) IDE0 Task File Data This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 80H. See Section 9.7.25 for bit definitions. 9.2.2 IDE0 Task File Register 1 Address Offset: 04H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Task File Command + Status IDE0 Task File Device+Head IDE0 Task File Cylinder High IDE0 Task File Cylinder Low This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 84H. See Section 9.7.26 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 63 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.3 Internal Register Space - Base Address 1 These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space. Address Offset Register Name 31 16 Reserved IDE0 TF Device Control Auxiliary Status Reserved 15 00 Reserved Access Type 00H R/W Table 9-3: SiI 0680A Internal Register Space - Base Address 1 9.3.1 IDE0 Task File Register 2 Address Offset: 00H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved IDE0 Task File Device Control IDE0 Task File Auxiliary Status Reserved Reserved This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset 88H. See Section 9.7.27 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 64 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.4 Internal Register Space - Base Address 2 These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space. Address Offset Register Name 31 16 IDE1 TF Starting Sector Number IDE1 TF Command+Status IDE1 TF Sector Count IDE1 TF Device+Head IDE1 TF Features IDE1 TF Error IDE1 TF Cylinder High 15 00 IDE1 TF Data IDE1 TF Cylinder Low Access Type 00H 04H R/W R/W Table 9-4: SiI 0680A Internal Register Space - Base Address 2 9.4.1 IDE1 Task File Register 0 Address Offset: 00H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Task File Starting Sector Number IDE1 Task File Sector Count IDE1 Task File Features (W) IDE1 Task File Error (R) IDE1 Task File Data This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset C0H. See Section 9.7.39 for bit definitions. 9.4.2 IDE1 Task File Register 1 Address Offset: 04H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Task File Command + Status IDE1 Task File Device+Head IDE1 Task File Cylinder High IDE1 Task File Cylinder Low This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset C4H. See Section 9.7.40 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 65 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.5 Internal Register Space - Base Address 3 These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space. Address Offset Register Name 31 16 Reserved IDE1 TF Device Control Auxiliary Status Reserved 15 00 Reserved Access Type 00H R/W Table 9-5: SiI 0680A Internal Register Space - Base Address 3 9.5.1 IDE1 Task File Register 2 Address Offset: 00H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved IDE1 Task File Device Control IDE1 Task File Auxiliary Status Reserved Reserved This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. The register bits are also mapped to Base Address 5, Offset C8H. See Section 9.7.41 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 66 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.6 Internal Register Space - Base Address 4 These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space. Address Offset Register Name 31 16 Reserved PCI Bus Master Status - IDE0 Software Data 15 00 PCI Bus Master Command - IDE0 Access Type 00H 04H 08H 0CH R/W R/W PRD Table Address - IDE0 Reserved PCI Bus Master Status - IDE1 Reserved PCI Bus Master Command - IDE1 R/W R/W PRD Table Address - IDE1 Table 9-6: SiI 0680A Internal Register Space - Base Address 4 9.6.1 PCI Bus Master - IDE0 Address Offset: 00H Access Type: Read/Write Reset Value: 0x0000_XX00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved IDE0 DMA Comp PBM DMA Cap 1 PBM DMA Cap 0 IDE Watchdog PBM Simplex IDE1 DMA Comp Software Reserved This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. See Section 9.7.1 for bit definitions. 9.6.2 PRD Table Address - IDE0 Address Offset: 04H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Table Address - IDE0 Reserved This register defines the PRD Table Address register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped to PCI Configuration Space, Offset 74H and Base Address 5, Offset 04H. See Section 9.7.2 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 67 PBM Enable PBM Active PBM Rd-Wr PBM Error Reserved Reserved SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.6.3 PCI Bus Master - IDE1 Address Offset: 08H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PBM Simplex PBM Enable PBM Active PBM Rd-Wr PBM Error Reserved IDE1 DMA Comp PBM DMA Cap 1 PBM DMA Cap 0 Reserved Reserved Reserved Reserved Reserved This register defines the PCI bus master register for IDE Channel #1 in the SiI 0680A. See Section 9.7.3 for bit definitions. 9.6.4 PRD Table Address - IDE1 Address Offset: 0CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Table Address - IDE1 This register defines the PRD Table Address register for IDE Channel #1 in the SiI 0680A. The register bits are also mapped to PCI Configuration Space, Offset 7CH and Base Address 5, Offset 0CH. See Section 9.7.4 for bit definitions. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 68 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7 Internal Register Space - Base Address 5 These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI Memory space. The Base Address 5 can be disabled by setting input BA5_EN to low Address Offset Register Name 31 16 Reserved PCI Bus Master Status - IDE0 Software Data 15 00 PCI Bus Master Command - IDE0 Access Type 00H 04H 08H 0CH 10H R/W R/W PRD Table Address - IDE0 Reserved PCI Bus Master Status - IDE1 Reserved PCI Bus Master Command - IDE1 R/W R/W PRD Table Address - IDE1 PCI Bus Master Status - IDE1 PCI Bus Master Status2 - IDE0 Software Data PCI Bus Master Command2 - IDE0 R/W 14H 18H Reserved Reserved PCI Bus Master Status2 - IDE1 Reserved PRD Address - IDE0 PCI Bus Master Byte Count - IDE0 PRD Address - IDE1 PCI Bus Master Byte Count - IDE1 Reserved Reserved Reserved Reserved FIFO Valid Byte Count - IDE0 FIFO Valid Byte Count - IDE1 System Configuration Status System Software Data FLASH Memory Address - Command and Status Reserved Flash Memory Data FIFO Wr Request Control - IDE0 FIFO Wr Request Control - IDE1 FIFO Rd Request Control - IDE0 FIFO Rd Request Control - IDE1 Reserved PCI Bus Master Command2 - IDE1 R/W 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W System Command EEPROM Memory Address - Command and Status Reserved FIFO Port - IDE0 EEPROM Memory Data (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 69 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Address Offset Register Name 31 16 Reserved FIFO Byte1 Write Pointer - IDE0 FIFO Byte3 Write Pointer - IDE0 FIFO Byte1 Read Pointer - IDE0 FIFO Byte3 Read Pointer - IDE0 FIFO Byte0 Write Pointer - IDE0 FIFO Byte2 Write Pointer - IDE0 FIFO Byte0 Read Pointer - IDE0 FIFO Byte2 Read Pointer - IDE0 15 00 Access Type 64H 68H 6CH 70H 74H 78H 7CH 80H 84H 88H FIFO Byte1 Write Pointer - IDE1 FIFO Byte3 Write Pointer - IDE1 IDE0 TF Starting Sector Number IDE0 TF Command+Status Reserved R R R/W FIFO Byte0 Read Pointer - IDE1 FIFO Byte2 Read Pointer - IDE1 IDE0 TF Data IDE0 TF Cylinder Low Reserved R R R/W R/W R/W FIFO Port - IDE1 Reserved FIFO Byte1 Read Pointer - IDE1 FIFO Byte3 Read Pointer - IDE1 IDE0 TF Sector Count IDE0 TF Device+Head IDE0 TF Device Control Auxiliary Status FIFO Byte0 Write Pointer - IDE1 FIFO Byte2 Write Pointer - IDE1 IDE0 TF Features IDE0 TF Error IDE0 TF Cylinder High Reserved 8CH 90H IDE0 TF Starting Sector Number2 IDE0 TF Cmd+Sts2 IDE0 Read Ahead Data IDE0 TF Sector Count2 IDE0 TF Device+Head2 IDE0 TF Features2 IDE0 TF Error2 IDE0 TF Cylinder High2 Reserved R/W R/W 94H 98H 9CH A0H A4H A8H ACH B0H B4H B8H BCH C0H C4H C8H IDE0 TF Cylinder Low2 R/W R/W Reserved IDE0 Virtual DMA/PIO Read Ahead Byte Count IDE0 TF Timing IDE0 Device 1 PIO Timing IDE0 Device 1 DMA Timing IDE0 Device 1 UDMA Timing IDE0 Config + Status IDE0 + Status Cmd R/W R/W R/W R/W R/W IDE0 Device 0 PIO Timing IDE0 Device 0 DMA Timing IDE0 Device 0 UDMA Timing IDE0 Test Register Reserved Reserved Reserved IDE1 TF Starting Sector Number IDE1 TF Command+Status Reserved IDE1 TF Sector Count IDE1 TF Device+Head IDE1 TF Device Control Auxiliary Status IDE1 TF Features IDE1 TF Error IDE1 TF Cylinder High IDE1 TF Data IDE1 TF Cylinder Low IDE0 Data Transfer Mode R/W R/W R/W R/W Reserved (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 70 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Address Offset Register Name 31 16 IDE1 Read Ahead Data IDE1 TF Starting Sector Number2 IDE1 TF Cmd+Sts2 IDE1 TF Sector Count2 IDE1 TF Device+Head2 IDE1 TF Features2 IDE1 TF Error2 IDE1 TF Cylinder High2 Reserved 15 00 Access Type CCH D0H R/W R/W D4H D8H DCH E0H E4H E8H ECH F0H F4H F8H FCH IDE1 TF Cylinder Low2 R/W R/W Reserved IDE1 Virtual DMA/PIO Read Ahead Byte Count IDE1 TF Timing IDE1 Device 1 PIO Timing IDE1 Device 1 DMA Timing IDE1 Device 1 UDMA Timing IDE1 Config + Status IDE1 + Status Cmd R/W R/W R/W R/W R/W IDE1 Device 0 PIO Timing IDE1 Device 0 DMA Timing IDE1 Device 0 UDMA Timing IDE1 Test Register Reserved Reserved Reserved Table 9-7: SiI 0680A Internal Register Space - Base Address 5 IDE1 Data Transfer Mode R/W - 9.7.1 PCI Bus Master - IDE0 Address Offset: 00H Access Type: Read/Write Reset Value: 0x0000_XX00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved IDE0 DMA Comp PBM DMA Cap 1 PBM DMA Cap 0 IDE Watchdog PBM Simplex IDE1 DMA Comp Software Reserved This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. The register bits are defined below. * * * * * * Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [23]: PBM Simplex (R) - PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to indicate that both IDE channels can operate as PCI bus master at any time. Bit [22]: PBM DMA Cap 1 (R/W) - PCI Bus Master DMA Capable - Device 1. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [21]: PBM DMA Cap 0 (R/W) - PCI Bus Master DMA Capable - Device 0. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [20:19]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [18]: IDE0 DMA Comp (R/W1C) - IDE0 DMA Completion Interrupt. During write DMA operation, This bit set indicates that the IDE0 interrupt has been asserted and all data has been written to system memory. During Read DMA, This bit set indicates that the IDE0 interrupt has been asserted. SiI-DS-0069-C 71 (c) 2006 Silicon Image, Inc. PBM Enable PBM Active PBM Rd-Wr PBM Error Reserved Reserved SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit reflects IDE0 interrupt line. Bit [17]: PBM Error (R/W1C) - PCI Bus Master Error - IDE0. This bit set indicates that a PCI bus error occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI Configuration space. Bit [16]: PBM Active (R) - PCI Bus Master Active - IDE0. This bit set indicates that the SiI 0680A is currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have completed or PBM Enable bit is not set. Bit[15] : IDE Watchdog Timer Status ( R ) - This bit is an Ored result of bit 12 in IDE0 Task File Timing + Configuration + Status and bit 12 of IDE1 Task File Timing + Configuration + Status registers. When set indicates that either IDE0 or IDE1 Watchdog timer has expired. Bit[14] : IDE1 Interrupt Status ( R ) - This bit is a copy of Bit[18] IDE1 DMA Completion Interrupt in PCI Bus Master - IDE1. Bit [13:08]: Software Data (R/W) - System Software Data Storage. This bit field is used for read/write data storage by the system. The properties of this bit field are detailed below. Bit Location [13:12] [11:10] [09:08] Default XXB 00B XXB Description Not cleared by any reset Cleared by PCI reset Cleared only by a D0-D3 power state change * * * * * Table 9-8: Software Data Byte, Base Address 5, Offset 00H * * * * Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [03]: PBM Rd-Wr (R/W) - PCI Bus Master Read-Write Control. This bit is set to specify a DMA write operation from IDE0 to system memory. This bit is cleared to specify a DMA read operation from system memory to an IDE0 device. Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [00]: PBM Enable (R/W) - PCI Bus Master Enable - IDE0. This bit is set to enable PCI bus master operations for IDE Channel #0. PCI bus master operations can be halted by clearing this bit, but will erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be aborted and the data discarded. While this bit is set, accessing IDE0 Task File or PIO data registers will be terminated with Target-Abort. 9.7.2 PRD Table Address - IDE0 Address Offset: 04H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Table Address - IDE0 Reserved This register defines the PRD Table Address register for IDE Channel #0 in the SiI 0680A. The register bits are defined below. * * Bit [31:02]: PRD Table Address (R/W) - Physical Region Descriptor Table Address. This bit field defines the Descriptor Table base address. Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 72 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.3 PCI Bus Master - IDE1 Address Offset: 08H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PBM Simplex PBM Enable PBM Active PBM Rd-Wr PBM Error Reserved IDE1 DMA Comp PBM DMA Cap 1 PBM DMA Cap 0 Reserved Reserved Reserved Reserved Reserved This register defines the PCI bus master register for IDE Channel #1 in the SiI 0680A. The register bits are defined below. * * * * * * Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [23]: PBM Simplex (R) - PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to indicate that both IDE channels can operate as PCI bus master at any time. Bit [22]: PBM DMA Cap 1 (R/W) - PCI Bus Master DMA Capable - Device 1. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [21]: PBM DMA Cap 0 (R/W) - PCI Bus Master DMA Capable - Device 0. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [20:19]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [18]: IDE1 DMA Comp (R/W1C) - IDE1 DMA Completion Interrupt. During write DMA operation, this bit set indicates that the IDE1 interrupt has been asserted and all data has been written to system memory. During Read DMA, this bit set indicates that the IDE1 interrupt has been asserted. This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit reflects IDE1 interrupt line. Bit [17]: PBM Error (R/W1C) - PCI Bus Master Error - IDE1. This bit set indicates that a PCI bus error occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI Configuration space. Bit [16]: PBM Active (R) - PCI Bus Master Active - IDE1. This bit set indicates that the SiI 0680A is currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have completed or PBM Enable bit is not set. Bit [15:08]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [03]: PBM Rd-Wr (R/W) - PCI Bus Master Read-Write Control. This bit is set to specify a DMA write operation from IDE1 to system memory. This bit is cleared to specify a DMA read operation from system memory to an IDE1 device. Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [00]: PBM Enable (R/W) - PCI Bus Master Enable - IDE1. This bit is set to enable PCI bus master operations for IDE Channel #1. PCI bus master operations can be halted by clearing this bit, but will erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be aborted and the data discarded. While this bit is set, accessing IDE1 Task File or PIO data registers will be terminated with Target-Abort. * * * * * * * 9.7.4 PRD Table Address - IDE1 Address Offset: 0CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Table Address - IDE1 This register defines the PRD Table Address register for IDE Channel #1 in the SiI 0680A. The register bits are defined below. * * Bit [31:02]: PRD Table Address (R/W) - Physical Region Descriptor Table Address. This bit field defines the Descriptor Table base address. Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read. SiI-DS-0069-C 73 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.5 PCI Bus Master2 - IDE0 Address Offset: 10H Access Type: Read/Write Reset Value: 0x0008_xx00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 PBM DMA Cap 0 IDE1 PBM DMA Cap 1 IDE0 PBM DMA Cap 1 IDE0 PBM DMA Cap 0 IDE0 Watchdog IDE0 IDE1 Buffer Empty IDE1 PBM Simplex IDE0 PBM Simplex IDE0 Buffer Empty Software IDE0 PBM Active IDE0 DMA Comp IDE0 DMA Comp IDE0 PBM Error IDE Watchdog Reserved PBM Enable PBM Rd-Wr Reserved IDE1 PBM Active IDE1 DMA Comp IDE1 PBM Error IDE1 Watchdog This register defines the second PCI bus master register for IDE Channel #0 in the SiI 0680A. The system must access these register bits through this address to enable the Large Block Transfer Mode. The register bits are defined below. * * * * * * * * * * Bit [31:29]: (R) These bits are copy of PCI Bus Master IDE1 bits [23:21]. Bit [28]: IDE1 Watchdog (R ) . This bit is a copy of bit 12 in IDE1 Task File Timing + Configuration + Status register. Refer to chapter 9.7.47 for detail information. Bit [27] : IDE1 Buffer empty (R). This bit set indicates IDE1 FIFO is empty. Bit [26:24]: (R) These bits are copy of PCI Bus Master IDE1 bits [18:16]. Bit [23]: PBM Simplex (R) - PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to indicate that both IDE channels can operate as PCI bus master at any time. Bit [22]: PBM DMA Cap 1 (R/W) - PCI Bus Master DMA Capable - Device 1. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [21]: PBM DMA Cap 0 (R/W) - PCI Bus Master DMA Capable - Device 0. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [20]: IDE0 Watchdog (R ) : This bit is a copy of bit 12 in IDE0 Task File Timing + Configuration + Status register. Refer to chapter 9.7.33 for detail information. Bit [19] : IDE0 Buffer empty (R). This bit set indicates IDE0 FIFO is empty. Bit [18]: IDE0 DMA Comp (R/W1C) - IDE0 DMA Completion Interrupt. During write DMA operation, This bit set indicates that the IDE0 interrupt has been asserted and all data has been written to system memory. During Read DMA, This bit set indicates that the IDE0 interrupt has been asserted. This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit reflects IDE0 interrupt line. Bit [17]: PBM Error (R/W1C) - PCI Bus Master Error - IDE0. This bit set indicates that a PCI bus error occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI Configuration space. Bit [16]: PBM Active (R) - PCI Bus Master Active - IDE0. This bit set indicates that the SiI 0680A is currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have completed or PBM Enable bit is not set. Bit[15] : IDE Watchdog Timer Status ( R ) - This bit is an Ored result of bit 12 in IDE1 Task File Timing + Configuration + Status and bit 12 of IDE0 Task File Timing + Configuration + Status registers. When set indicates that either IDE0 or IDE1 Watchdog timer has expired. Bit[14] : IDE1 Interrupt Status ( R ) - This bit is a copy of Bit[18] IDE1 DMA Completion Interrupt in PCI Bus Master - IDE1. Bit [13:08]: Software Data (R/W) - System Software Data Storage. This bit field is used for read/write data storage by the system. The properties of this bit field are detailed below. Bit Location [13:12] [11:10] [09:08] Default XXB 00B XXB Description Not cleared by any reset Cleared by PCI reset Cleared only by a D0-D3 power state change * * * * * Table 9-9: Software Data Byte, Base Address 5, Offset 10H * Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read. SiI-DS-0069-C 74 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. * * * Bit [03]: PBM Rd-Wr (R/W) - PCI Bus Master Read-Write Control. This bit is set to specify a DMA write operation from IDE0 to system memory. This bit is cleared to specify a DMA read operation from system memory to an IDE0 device. Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [00]: PBM Enable (R/W) - PCI Bus Master Enable - IDE0. This bit is set to enable PCI bus master operations for IDE Channel #0. PCI bus master operations can be halted by clearing this bit, but will erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be aborted and the data discarded. While this bit is set, accessing IDE0 Task File or PIO data registers will be terminated with Target-Abort. 9.7.6 PCI Bus Master2 - IDE1 Address Offset: 18H Access Type: Read/Write Reset Value: 0x0008_xx00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Buffer Empty PBM Simplex PBM Enable PBM Active PBM Rd-Wr PBM Error Reserved IDE1 DMA Comp PBM DMA Cap 1 PBM DMA Cap 0 IDE1 Watchdog Reserved Reserved Reserved This register defines the second PCI bus master register for IDE Channel #1 in the SiI 0680A. The system must access these register bits through this address to enable the Large Block Transfer Mode. * * * * * * * Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [23]: PBM Simplex (R) - PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to indicate that both IDE channels can operate as PCI bus master at any time. Bit [22]: PBM DMA Cap 1 (R/W) - PCI Bus Master DMA Capable - Device 1. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [21]: PBM DMA Cap 0 (R/W) - PCI Bus Master DMA Capable - Device 0. This bit field has no effect. The device is always capable of DMA as a PCI bus master. Bit [20]: IDE1 Watchdog (R ) . This bit is a copy of bit 12 in IDE1 Task File Timing + Configuration + Status register. Refer to chapter 9.7.47 for detail information. Bit [19] : IDE1 Buffer empty (R). This bit set indicates IDE1 FIFO is empty. Bit [18]: IDE1 DMA Comp (R/W1C) - IDE1 DMA Completion Interrupt. During write DMA operation, this bit set indicates that the IDE1 interrupt has been asserted and all data has been written to system memory. During Read DMA, this bit set indicates that the IDE1 interrupt has been asserted. This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit reflects IDE1 interrupt line. Bit [17]: PBM Error (R/W1C) - PCI Bus Master Error - IDE1. This bit set indicates that a PCI bus error occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI Configuration space. Bit [16]: PBM Active (R) - PCI Bus Master Active - IDE1. This bit set indicates that the SiI 0680A is currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have completed or PBM Enable bit is not set. Bit [15:08]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [03]: PBM Rd-Wr (R/W) - PCI Bus Master Read-Write Control. This bit is set to specify a DMA write operation from IDE1 to system memory. This bit is cleared to specify a DMA read operation from system memory to an IDE1 device. Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [00]: PBM Enable (R/W) - PCI Bus Master Enable - IDE1. This bit is set to enable PCI bus master operations for IDE Channel #1. PCI bus master operations can be halted by clearing this bit, but will erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be aborted and the data discarded. While this bit is set, accessing IDE1 Task File or PIO data registers will be terminated with Target-Abort. * * * * * * * (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 75 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.7 PRD Address - IDE0 Address Offset: 20H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Address This register reflects the current DMA address and uses for diagnostic purposes only. * Bit [31:00]: PRD Address (R) - This field is the current DMA0 Address. 9.7.8 PCI Bus Master Byte Count - IDE0 Address Offset: 24H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 End of Table Byte Count High Byte Count Low This register defines the byte count register in the PCI bus master logic for IDE Channel #0 in the SiI 0680A. The register bits are defined below. * * * Bit [31]: End of Table (R). This bit set indicates that this is the last entry in the PRD table. Bit [30:16] Byte Count High (R). This bit field is the PRD entry byte count extension for Large Block Transfer Mode. Under generic mode, this bit field is reserved and returns zeros on a read. Bit [15:00] Byte Count Low (R). This bit field reflects the current DMA0 byte count value. 9.7.9 PRD Address - IDE1 Address Offset: 28H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PRD Address This register reflects the current DMA1 Address and uses for diagnostic purposes only. * Bit [31:00]: PRD Address (R) - This field is the current DMA1 Address. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 76 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.10 PCI Bus Master Byte Count - IDE1 Address Offset: 2CH Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 End of Table Byte Count High Byte Count Low This register defines the byte count register in the PCI bus master logic for IDE Channel #1 in the SiI 0680A. The register bits are defined below. * * * Bit [31]: End of Table (R). This bit set indicates that this is the last entry in the PRD table. Bit [30:16] Byte Count High (R). This bit field is the PRD entry byte count extension for Large Block Transfer Mode. Under generic mode, this bit field is reserved and returns zeros on a read. Bit [15:00] Byte Count Low (R). This bit field reflects the current DMA1 byte count value. 9.7.11 FIFO Valid Byte Count and Control - IDE0 Address Offset: 40H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved FIFO Valid Byte Count - IDE0 Reserved FIFO Wr Req Ctrl - IDE0 Reserved FIFO Rd Req Ctrl - IDE0 This register defines the FIFO valid byte count register and PCI bus request control for IDE Channel #0 in the SiI 0680A. The register bits are defined below. * * * * Bit [31:25]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [24:16]: FIFO Valid Byte Count - IDE0 (R). This bit field provides the valid byte count for the data FIFO for IDE Channel #0. A value of 000H indicates empty, while a value of 100H indicates a full FIFO with 256 bytes. Bit [15:14]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [13:08]: FIFO Wr Req Ctrl - IDE0 (R/W) - FIFO Write Request Control. This bit field defines the FIFO threshold to assign DMA0 priority when requesting a PCI bus for a write operation. A value of 00H indicates that DMA0 write request priority is set to 1 whenever the FIFO contains greater than zero DWords, while a value of 3F H indicates that DMA0 write request priority is set to 1 whenever the FIFO contains greater than 63 Dwords. This bit field is useful when two DMA channels are competing for accessing PCI bus. When the two DMA channels request the PCI bus at the same time, the one with the higher priority will have the bus when it's granted to the SiI 0680A. If the two DMA channels have the same priority, the channel that had the bus last will have the bus when it's granted to the SiI 0680A. When one DMA channel is controlling the PCI bus, and the other channel requests the PCI bus, if the channel currently controlling the PCI bus has the same or higher priority, it remains controlling the bus. However, if the channel requesting the PCI bus has higher priority, the lower priority channel terminates the PCI transaction, yielding the bus to the channel with the higher priority. * * Bit [07:06]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [05:00]: FIFO Rd Req Ctrl - IDE0 (R/W) - FIFO Read Request Control. This bit field defines the FIFO threshold to assign DMA0 priority when requesting a PCI for a read operation. A value of 00H indicates that DMA0 read request priority is set to 1 whenever the FIFO has greater than zero Dwords available space , while a value of 3F indicates that DMA0 read request priority is set to 1 whenever the FIFO has greater than 63 Dwords available space. This bit field is useful when two DMA channels are competing for accessing the PCI bus. SiI-DS-0069-C 77 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. When the two DMA channels request the PCI bus at the same time, the one with the higher priority will have the bus when it's granted to the SiI 0680A. If the two DMA channels have the same priority, the channel that had the bus last will have the bus when it's granted to the SiI 0680A. When one DMA channel is controlling the PCI bus, and the other channel requests the PCI bus, if the channel currently controlling the PCI bus has the same or higher priority, it remains controlling the bus. However, if the channel requesting the PCI bus has higher priority, the lower priority channel terminates the PCI transaction, yielding the bus to the channel with the higher priority. 9.7.12 FIFO Valid Byte Count and Control - IDE1 Address Offset: 44H Access Type: Read /Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved FIFO Valid Byte Count - IDE1 Reserved FIFO Wr Req Ctrl - IDE1 Reserved FIFO Rd Req Ctrl - IDE1 This register defines the FIFO valid byte count register and PCI bus request control for IDE Channel #1 in the SiI 0680A. The register bits are defined below. * * * * Bit [31:25]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [24:16]: FIFO Valid Byte Count - IDE1 (R). This bit field provides the valid byte count for the data FIFO for IDE Channel #1. A value of 000H indicates empty, while a value of 100H indicates a full FIFO with 256 bytes. Bit [15:14]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [13:08]: FIFO Wr Req Ctrl - IDE1 (R/W) - FIFO Write Request Control. This bit field defines the FIFO threshold to assign DMA1 priority when requesting a PCI for a write operation. A value of 00H indicates that DMA1 write request priority is set to 1 whenever the FIFO contains greater than zero DWords, while a value of 3F H indicates that DMA1 write request priority is set to 1 whenever the FIFO contains greater than 63 Dwords. This bit field is useful when two DMA channels are competing for accessing PCI bus. When the two DMA channels request the PCI bus at the same time, the one with the higher priority will have the bus when it's granted to the SiI 0680A. If the two DMA channels have the same priority, the channel that had the bus last will have the bus when it's granted to the SiI 0680A. When one DMA channel is controlling the PCI bus, and the other channel requests the PCI bus, if the channel currently controlling the PCI bus has the same or higher priority, it remains controlling the bus. However, if the channel requesting the PCI bus has higher priority, the lower priority channel terminates the PCI transaction, yielding the bus to the channel with the higher priority. * * Bit [07:06]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [05:00]: FIFO Rd Req Ctrl - IDE1 (R/W) - FIFO Read Request Control. This bit field defines the FIFO threshold to assign DMA1 priority when requesting a PCI for a read operation. A value of 00H indicates that DMA1 read request priority is set to 1 whenever the FIFO has greater than zero Dwords available space , while a value of 3F indicates that DMA1 read request priority is set to 1 whenever the FIFO has greater than 63 Dwords available space. This bit field is useful when two DMA channels are competing for accessing the PCI bus. When the two DMA channels request the PCI bus at the same time, the one with the higher priority will have the bus when it's granted to the SiI 0680A. If the two DMA channels have the same priority, the channel that had the bus last will have the bus when it's granted to the SiI 0680A. When one DMA channel is controlling the PCI bus, and the other channel requests the PCI bus, if the channel currently controlling the PCI bus has the same or higher priority, it remains controlling the bus. However, if the channel requesting the PCI bus has higher priority, the lower priority channel terminates the PCI transaction, yielding the bus to the channel with the higher priority. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 78 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.13 System Configuration Status - Command Address Offset: 48H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Module Rst IDE1 Module Rst FF0 Module Rst IDE Clk Select IDE1 Int Block IDE0 Int Block Reserved BA5_EN FF1 Module Rst Reserved Reserved PBM Module Rst ARB Module Rst Reserved This register defines the system configuration status and command register for the SiI 0680A. The register bits are defined below. * Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [23]: IDE1 Int Block (R/W) - IDE1 Interrupt Block. This bit is set to block interrupts from the IDE Channel #1 to the PCI bus. * Bit [22]: IDE0 Int Block (R/W) - IDE0 Interrupt Block. This bit is set to block interrupts from the IDE Channel #0 to the PCI bus. * Bit [21:20]: IDE Clk Select (R/W) - IDE Clock Frequency Select. This bit field is used set the IDE clock frequency for both IDE modules: 00B = 100 MHz; 01B = 133 MHz; 10B = PCI Clock x 2; and, 11B = IDE Clock Disabled. * Bit [19:17]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [16]: BA5_EN (R) - Base Address 5 Enable. This bit reflects input pin BA5_EN. * Bit [15:08]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [07]: IDE0 Module Rst (R/W) - IDE0 Module Reset. This bit is set to reset the interface logic for the IDE Channel #0. * Bit [06]: IDE1 Module Rst (R/W) - IDE1 Module Reset. This bit is set to reset the interface logic for the IDE Channel #1. * Bit [05]: FF0 Module Rst (R/W) - FF0 Module Reset. This bit is set to reset the logic in the FIFO for IDE Channel #0. * Bit [04]: FF1 Module Rst (R/W) - FF1 Module Reset. This bit is set to reset the logic in the FIFO for IDE Channel #1. * Bit [03:02]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [01]: ARB Module Rst (R/W) - ARB Module Reset. This bit is set to reset the internal logic for the PCI-IDE arbiter. * Bit [00]: PBM Module Rst (R/W) - PBM Module Reset. This bit is set to reset the internal logic for the PCI bus master state machine. 9.7.14 System Software Data Register Address Offset: 4CH Access Type: Read/Write Reset Value: Undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 System Software Data This register is used by the software for non-resettable data storage. The contents are unknown on power-up and are never cleared by any type of reset. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 79 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.15 FLASH Memory Address - Command + Status Address Offset: 50H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Mem Access Type Mem Access Start Mem Init Done Reserved Memory Address Reserved This register defines the address and command/status register for FLASH memory interface in the SiI 0680A. The register bits are defined below. * * * * * * * Bit [31:28]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [27]: Memory Init Done (R) - This bit set indicates that the memory initialization sequence is done. The memory sequence is activated upon the release of reset. Bit [26]: Reserved (R) - This bit is reserved and returns an indeterminate value on a read. Bit [25]: Mem Access Start (R/W) - Memory Access Start. This bit is set to initiate an operation to FLASH memory. This bit is cleared by the chip when the operation is complete. Bit [24]: Mem Access Type (R/W) - Memory Access Type. This bit is set to define a read operation from FLASH memory. This bit is cleared to define a write operation to FLASH memory. Bit [23:19]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [18:00]: Memory Address (R/W). This bit field is programmed with the address for a FLASH memory read or write access. 9.7.16 FLASH Memory Data Address Offset: 54H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Memory Data This register defines the data register for FLASH memory interface in the SiI 0680A. The system writes to this register for a write operation to FLASH memory, and reads from this register on a read operation from FLASH memory. * * Bit [31:08]: Reserved (R). Bit [07:00]: Memory Data (R/W) - FLASH Memory Data. This bit field is used for FLASH write data on a write operation, and returns the FLASH read data on a read operation. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 80 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.17 EEPROM Memory Address - Command + Status Address Offset: 58H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Mem Error Reserved Mem Access Type Mem Access Start Mem Init Done Reserved Mem Address Reserved This register defines the address and command/status register for EEPROM memory interface in the SiI 0680A. The register bits are defined below. * * * * * * * * Bit [31:29]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [28]: Mem Error (R/W1C) - Memory Access Error. This bit set indicates that the EEPROM interface logic detects three NAKs from the memory device. Bit [27]: Mem Init Done (R) - Memory Initialization Done. This bit set indicates that the memory initialization sequence is done. The memory initialization sequence is activated upon the release of reset. Bit [26]: Reserved (R) This bit is reserved and returns an indeterminate value on a read. Bit [25]: Mem Access Start (R/W) - Memory Access Start. This bit is set to initiate an operation to EEPROM memory. This bit is cleared by the chip when the operation is complete. Bit [24]: Mem Access Type (R/W) - Memory Access Type. This bit is set to define a read operation from EEPROM memory. This bit is cleared to define a write operation to EEPROM memory. Bit [23:16]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [15:00]: Memory Address (R/W). This bit field is programmed with the address for an EEPROM memory read or write access. 9.7.18 EEPROM Memory Data Address Offset: 5CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved Memory Data This register defines the data register for EEPROM memory interface in the SiI 0680A. The system writes to this register for a write operation to EEPROM memory, and reads from this register on a read operation from EEPROM memory. The register bits are defined below. * * Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [07:00]: Memory Data (R/W) - EEPROM Memory Data. This bit field is used for EEPROM write data on a write operation, and returns the EEPROM read data on a read operation. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 81 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.19 FIFO Port - IDE0 Address Offset: 60H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FIFO Port - IDE0 This register defines the direct access register for the FIFO port of IDE Channel #0 in the SiI 0680A. This register is used for hardware debugging purposes only. The system can read from or write to this register for direct access to the data FIFO between the PCI bus and IDE Channel #0. While DMA0 is active, reading this register will be terminated with TargetAbort. 9.7.20 FIFO Pointers1- IDE0 Address Offset: 68H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FIFO Byte 1 Wr Pointer - IDE0 FIFO Byte 1 Rd Pointer - IDE0 FIFO Byte 0 Wr Pointer - IDE0 FIFO Byte 0 Rd Pointer - IDE0 This register provides visibility into the data FIFO for IDE Channel #0 in the SiI 0680A. The data FIFO is organized as a four byte-wide x 64 deep memory array. There are separate write and read pointer for each of the byte slices. This register is used for hardware debugging purposes only. The register bits are defined below. * Bit [31:24]: FIFO Byte 1 Wr Pointer - IDE0 (R) FIFO Byte 1 Write Pointer. This bit field provides the status on the write pointer for Byte 1. * Bit [23:16]: FIFO Byte 1 Rd Pointer - IDE0 (R) FIFO Byte 1 Read Pointer. This bit field provides the status on the read pointer for Byte 1. * Bit [15:08]: FIFO Byte 0 Wr Pointer - IDE0 (R) FIFO Byte 0 Write Pointer. This bit field provides the status on the write pointer for Byte 0. * Bit [07:00]: FIFO Byte 0 Rd Pointer - IDE0 (R) FIFO Byte 0 Read Pointer. This bit field provides the status on the read pointer for Byte 0. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 82 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.21 FIFO Pointers2- IDE0 Address Offset: 6CH Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FIFO Byte 3 Wr Pointer - IDE0 FIFO Byte 3 Rd Pointer - IDE0 FIFO Byte 2 Wr Pointer - IDE0 FIFO Byte 2 Rd Pointer - IDE0 This register provides visibility into the data FIFO for IDE Channel #0 in the SiI 0680A. The data FIFO is organized as a four byte-wide x 64 deep memory array. There are separate write and read pointer for each of the byte slices. This register is used for hardware debugging purposes only. The register bits are defined below. * Bit [31:24]: FIFO Byte 3 Wr Pointer - IDE0 (R) FIFO Byte 3 Write Pointer. This bit field provides the status on the write pointer for Byte 3. * Bit [23:16]: FIFO Byte 3 Rd Pointer - IDE0 (R) FIFO Byte 3 Read Pointer. This bit field provides the status on the read pointer for Byte 3. * Bit [15:08]: FIFO Byte 2 Wr Pointer - IDE0 (R) FIFO Byte 2 Write Pointer. This bit field provides the status on the write pointer for Byte 2. * Bit [07:00]: FIFO Byte 2 Rd Pointer - IDE0 (R) FIFO Byte 2 Read Pointer. This bit field provides the status on the read pointer for Byte 2. 9.7.22 FIFO Port - IDE1 Address Offset: 70H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FIFO Port - IDE1 This register defines the direct access register for the FIFO port of IDE Channel #1 in the SiI 0680A. This register is used for hardware debugging purposes only. The system can read from or write to this register for direct access to the data FIFO between the PCI bus and IDE Channel #1. While DMA1 is active, reading this register will be terminated with TargetAbort. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 83 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.23 FIFO Pointers1- IDE1 Address Offset: 78H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FIFO Byte 1 Wr Pointer - IDE1 FIFO Byte 1 Rd Pointer - IDE1 FIFO Byte 0 Wr Pointer - IDE1 FIFO Byte 0 Rd Pointer - IDE1 This register provides visibility into the data FIFO for IDE Channel #1 in the SiI 0680A. The data FIFO is organized as a four byte-wide x 64 deep memory array. There are separate write and read pointer for each of the byte slices. This register is used for hardware debugging purposes only. The register bits are defined below. * Bit [31:24]: FIFO Byte 1 Wr Pointer - IDE1 (R) FIFO Byte 1 Write Pointer. This bit field provides the status on the write pointer for Byte 1. * Bit [23:16]: FIFO Byte 1 Rd Pointer - IDE1 (R) FIFO Byte 1 Read Pointer. This bit field provides the status on the read pointer for Byte 1. * Bit [15:08]: FIFO Byte 0 Wr Pointer - IDE1 (R) FIFO Byte 0 Write Pointer. This bit field provides the status on the write pointer for Byte 0. * Bit [07:00]: FIFO Byte 0 Rd Pointer - IDE1 (R) FIFO Byte 0 Read Pointer. This bit field provides the status on the read pointer for Byte 0. 9.7.24 FIFO Pointers2- IDE1 Address Offset: 7CH Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 FIFO Byte 3 Wr Pointer - IDE1 FIFO Byte 3 Rd Pointer - IDE1 FIFO Byte 2 Wr Pointer - IDE1 FIFO Byte 2 Rd Pointer - IDE1 This register provides visibility into the data FIFO for IDE Channel #1 in the SiI 0680A. The data FIFO is organized as a four byte-wide x 64 deep memory array. There are separate write and read pointer for each of the byte slices. This register is used for hardware debugging purposes only. The register bits are defined below. * Bit [31:24]: FIFO Byte 3 Wr Pointer - IDE1 (R) FIFO Byte 3 Write Pointer. This bit field provides the status on the write pointer for Byte 3. * Bit [23:16]: FIFO Byte 3 Rd Pointer - IDE1 (R) FIFO Byte 3 Read Pointer. This bit field provides the status on the read pointer for Byte 3. * Bit [15:08]: FIFO Byte 2 Wr Pointer - IDE1 (R) FIFO Byte 2 Write Pointer. This bit field provides the status on the write pointer for Byte 2. * Bit [07:00]: FIFO Byte 2 Rd Pointer - IDE1 (R) FIFO Byte 2 Read Pointer. This bit field provides the status on the read pointer for Byte 2. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 84 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.25 IDE0 Task File Register 0 Address Offset: 80H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Task File Starting Sector Number IDE0 Task File Sector Count IDE0 Task File Features (W) IDE0 Task File Error (R) IDE0 Task File Data This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. Access to the individual bytes of this register is determined by the PCI bus Byte Enables at the time of the read or write operation. The register bits are defined below. * Bit [31:00]: IDE0 Task File Data (R/W). This bit field defines the IDE0 Task File Data register. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 0 must be active. To access 32-bit Task File Data, the Byte Enables for all four bytes must be active. Bit [31:24]: IDE0 Task File Starting Sector Number (R/W). This bit field defines the IDE0 Task File Starting Sector Number register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. Bit [23:16]: IDE0 Task File Sector Count (R/W). This bit field defines the IDE0 Task File Sector Count register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. Bit [15:08]: IDE0 Task File Features (W). This write-only bit field defines the IDE0 Task File Features register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. Bit [15:08]: IDE0 Task File Error (R). This read-only bit field defines the IDE0 Task File Error register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. * * * * 9.7.26 IDE0 Task File Register 1 Address Offset: 84H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Task File Command + Status IDE0 Task File Device+Head IDE0 Task File Cylinder High IDE0 Task File Cylinder Low This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. Access to these bit field is permitted if the PCI bus Byte Enable is active for one byte only. The register bits are defined below. * * * * * Bit [31:24]: register. Bit [31:24]: Bit [23:16]: register. Bit [15:08]: Bit [07:00]: IDE0 Task File Command (W). This write-only bit field defines the IDE0 Task File Command IDE0 Task File Status (R). This read-only bit field defines the IDE0 Task File Status register. IDE0 Task File Device+Head (R/W). This bit field defines the IDE0 Task File Device and Head IDE0 Task File Cylinder High (R/W). This bit field defines the IDE0 Task File Cylinder High register. IDE0 Task File Cylinder Low (R/W). This bit field defines the IDE0 Task File Cylinder Low register. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 85 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.27 IDE0 Task File Register 2 Address Offset: 88H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved IDE0 Task File Device Control IDE0 Task File Auxiliary Status Reserved Reserved This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. Access to these bit fields is permitted if the PCI bus Byte Enable is active for one byte only. The register bits are defined below. * * * * Bit [31:24]: Bit [23:16]: Bit [23:16]: register. Bit [15:00]: Reserved (R). This bit field is reserved and returns zeros on a read. IDE0 Task File Device Control (W). This bit field defines the IDE0 Task File Device Control register. IDE0 Task File Auxiliary Status (R). This bit field defines the IDE0 Task File Auxiliary Status Reserved (R). This bit field is reserved and returns zeros on a read. 9.7.28 IDE0 Read Ahead Data Address Offset: 8CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Read Ahead Data This register defines the read ahead data port for PIO transfers on IDE Channel #0 in the SiI 0680A. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must be zero-aligned. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 86 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.29 IDE0 Task File Register 0 - Command Buffering Address Offset: 90H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Task File Starting Sector Number IDE0 Task File Sector Count IDE0 Task File Features (W) IDE0 Task File Error (R) IDE0 Task File Data This register defines one of the IDE Channel #0 Task File registers used for Command Buffered accesses in the SiI 0680A. Access to the individual bytes of this register is determined by the PCI bus Byte Enables at the time of the read or write operation. The register bits are defined below. * Bit [31:00]: IDE0 Task File Data (R/W). This bit field defines the IDE0 Task File Data register. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 0 must be active. To access 32-bit Task File Data, the Byte Enables for all four bytes must be active. Bit [31:24]: IDE0 Task File Starting Sector Number (R/W). This bit field defines the IDE0 Task File Starting Sector Number register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 3 is active. Bit [23:16]: IDE0 Task File Sector Count (R/W). This bit field defines the IDE0 Task File Sector Count register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 2 is active. Bit [15:08]: IDE0 Task File Features (W). This write-only bit field defines the IDE0 Task File Features register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active. Bit [15:08]: IDE0 Task File Error (R). This read-only bit field defines the IDE0 Task File Error register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active. * * * * 9.7.30 IDE0 Task File Register 1 - Command Buffering Address Offset: 94H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Task File Command + Status IDE0 Task File Device+Head IDE0 Task File Cylinder High IDE0 Task File Cylinder Low This register defines one of the IDE Channel #0 Task File registers used for Command Buffered accesses in the SiI 0680A. The register bits are defined below. * * * * * Bit [31:24]: register. Bit [31:24]: Bit [23:16]: register. Bit [15:08]: Bit [07:00]: IDE0 Task File Command (W). This write-only bit field defines the IDE0 Task File Command IDE0 Task File Status (R). This read-only bit field defines the IDE0 Task File Status register. IDE0 Task File Device+Head (R/W). This bit field defines the IDE0 Task File Device and Head IDE0 Task File Cylinder High (R/W). This bit field defines the IDE0 Task File Cylinder High register. IDE0 Task File Cylinder Low (R/W). This bit field defines the IDE0 Task File Cylinder Low register. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 87 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.31 IDE0 UDMA Control Address Offset: 98H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved * This bit field is reserved and returns an indeterminate value on a read. 9.7.32 IDE0 Virtual DMA/PIO Read Ahead Byte Count Address Offset: 9CH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Virtual DMA/PIO Read Ahead Byte Count Not Used This register defines the read ahead byte count register for Virtual DMA and PIO Read Ahead transfers on IDE Channel #0 in the SiI 0680A. In Virtual DMA mode (PCI bus master DMA with PIO transfers on the IDE), all 32 bits are used as the wordaligned byte count. In PIO Read Ahead mode, only the lower 16 bits are used as the word-aligned byte count. The higher 16 bits must be programmed 0x0000. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 88 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.33 IDE0 Task File Timing + Configuration + Status Address Offset: A0H Access Type: Read/Write Reset Value: 0x6515_0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Watchdog Timeout IORDY Monitoring Watchdog Int Ena Buffered Cmd Channel Rst Reserved Reserved Cable 80 Addr Setup Count Active Count Recovery Count Reserved Channel Tri-State Interrupt Status Virtual DMA Int Watchdog Ena This register defines the task file timing register for IDE Channel #0 in the SiI 0680A. The register bits are defined below. * * * * * * * Bit [31:28]: Addr Setup Count (R/W) - IDE0 Address Setup Time Count. This bit field is used for adjusting the address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on programming the timing register. Bit [27:22]: Active Count (R/W) - IDE0 DIOR_N and DIOW_N Active Time Count. This bit field is used for adjusting the active time of IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on programming this timing register. Bit [21:16]: Recovery Count (R/W) - IDE0 DIOR_N and DIOW_N Recovery Time Count. This bit field is used for adjusting the recovery time of IDE0_DIOR_N and IDE0_DIOW_N. See Chapter 11 for details on programming this timing register. Bit [15]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [14] : Watchdog Int Ena ( R/W ) - IDE0 Watchdog Interrupt Enable. This bit is set to enable Interrupt when Watchdog timer expired. Bit [13]: Watchdog Ena (R/W) - IDE0 Watchdog Timer Enable. This bit is set to enable the watchdog timer for IDE0. This bit is cleared to disable the watchdog timer. Bit [12]: Watchdog Timeout (R/W1C) - IDE0 Watchdog Timer Timeout. This bit set indicates that the watchdog timer for IDE0 timed out. When enabled, and IORDY monitoring bit is also enabled, during IDE0 PIO opeartion, the watchdog counter starts counting when IORDY signal is deasserted. If after 256 PCI clocks cycles, the IORDY signal is still deasserted, the Watchdog Timer is expires, and this bit is set and the SiI 0680A continue its operation and stop monitoring IORDY signal. Software writes one to clear this bit. Once this bit is cleared, the SiI 0680A starts monitoring IORDY on channel 0 again. Bit [11]: Interrupt Status (R) - IDE0 Interrupt Status. This bit set indicates that an interrupt is pending on IDE0. This bit provides real-time status of the IDE0 interrupt pin. Bit [10]: Virtual DMA Int (R) - IDE0 Virtual DMA Completion Interrupt. This bit set indicates that the Virtual DMA data transfer has completed. This bit is cleared when bit[0] PBM enable in PCI Bus Master - IDE0 is cleared . Bit [09]: IORDY Monitoring (R/W) - IDE0 IORDY Monitoring. When this bit is set, IORDY line is monitored for Task File accesses on channel 0. Bit [08:04]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [03]: Channel Tri-State (R/W) - IDE0 Channel Tri-State. This bit is set to tri-state the IDE Channel #0 bus. This bit is cleared for normal operations. Bit [02]: Channel Rst (R/W) - IDE0 Channel Reset. When this bit is set, IDE Channel #0 RST signal is asserted. Bit [01]: Buffered Cmd (R) - IDE0 Buffered Command Active. This bit set indicates that a Buffered Command is currently active. This bit is set when the first command byte is written to the command buffer. This bit is cleared when all of the task file bytes, including the command byte, have been written to the device. Bit [00]: Cable 80 (R) - IDE0 Cable 80 Detection. This bit provides real-time status of the inverted version of the IDE0_CBLID_N pin. When set, it indicates that 80 pin cable is detected. * * * * * * * * (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 89 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.34 IDE0 PIO Timing Address Offset: A4H Access Type: Read/Write Reset Value: 0x62DD_62DD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the PIO timing register for IDE Channel #0 in the SiI 0680A. See chapter 11 for details on programming this timing register. The register bits are defined below. * * * * * * Bit [31:28]: Device 1 Addr Setup Count (R/W) - IDE0 Device 1 Address Setup Time Count for PIO Mode. This bit field is used for programming the address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N in PIO mode. Bit [27:22]: Device 1 Active Count (R/W) - IDE0 Device 1 DIOR_N and DIOW_N Active Time Count for PIO Mode. This bit field is used for programming the active time of IDE0_DIOR_N and IDE0_DIOW_N in PIO mode. Bit [21:16]: Device 1 Recovery Count (R/W) - IDE0 Device 1 DIOR_N and DIOW_N Recovery Time Count for PIO Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in PIO mode. Bit [15:12]: Device 0 Addr Setup Count (R/W) - IDE0 Device 0 Address Setup Time Count for PIO Mode. This bit field is used for programming the address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N in PIO mode Bit [11:06]: Device 0 Active Count (R/W) - IDE0 Device 0 DIOR_N and DIOW_N Active Time Count for PIO Mode. This bit field is used for programming the active time of IDE0_DIOR_N and IDE0_DIOW_N in PIO mode. Bit [05:00]: Device 0 Recovery Count (R/W) - IDE0 Device 0 DIOR_N and DIOW_N Recovery Time Count for PIO Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in PIO mode. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 90 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.35 IDE0 DMA Timing Address Offset: A8H Access Type: Read/Write Reset Value: 0x4392_4392 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the DMA timing register for IDE Channel #0 in the SiI 0680A. See chapter 13 for details on programming this timing register. The register bits are defined below. * * * * * * Bit [31:28]: Device 1 Addr Setup Count (R/W) - IDE0 Device 1 Address Setup Time Count for DMA Mode. This bit field is used for programming the address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N in DMA mode. Bit [27:22]: Device 1 Active Count (R/W) - IDE0 Device 1 DIOR_N and DIOW_N Active Time Count for DMA Mode. This bit field is used for programming the active time of IDE0_DIOR_N and IDE0_DIOW_N in DMA mode. Bit [21:16]: Device 1 Recovery Count (R/W) - IDE0 Device 1 DIOR_N and DIOW_N Recovery Time Count for DMA Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in DMA mode. Bit [15:12]: Device 0 Addr Setup Count (R/W) - IDE0 Device 0 Address Setup Time Count for DMA Mode. This bit field is used for programming the address setup time relative to IDE0_DIOR_N and IDE0_DIOW_N in DMA mode. Bit [11:06]: Device 0 Active Count (R/W) - IDE0 Device 0 DIOR_N and DIOW_N Active Time Count for DMA Mode. This bit field is used for programming the active time of IDE0_DIOR_N and IDE0_DIOW_N in DMA mode. Bit [05:00]: Device 0 Recovery Count (R/W) - IDE0 Device 0 DIOR_N and DIOW_N Recovery Time Count for DMA Mode. This bit field is used for programming the recovery time of IDE0_DIOR_N and IDE0_DIOW_N in DMA mode. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 91 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.36 IDE0 UDMA Timing Address Offset: ACH Access Type: Read/Write Reset Value: 0x4009_4009 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Data Input Delay Device 0 Data Input Delay Device 1 DSTROBE Delay Device 1 HSTROBE Delay Device 0 DSTROBE Delay Reserved Reserved Device 1 Cycle Time Count Device 0 HSTROBE Delay Device 0 Cycle Time Count This register defines the UDMA timing register for IDE Channel #0 in the SiI 0680A. See chapter 11 for details on programming this timing register. The register bits are defined below. * Bit [31:30]: Device 1 Data Input Delay (R/W) - IDE0 Device 1 Data Input Delay for UDMA Mode. This bit field is used for programming the data input delay in increments of 2 nsec in UDMA mode. * Bit [29:28]: Device 1 DSTROBE Delay (R/W) - IDE0 Device 1 DSTROBE Delay for UDMA Mode. This bit field is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode. * Bit [27:25]: Device 1 HSTROBE Delay (R/W) - IDE0 Device 1 HSTROBE Delay for UDMA Mode. This bit field is used for programming the HSTROBE output delay in increments of 2 nsec in UDMA mode. * Bit [24:23]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [22]: Reserved (R/W) - This bit field is reserved. * Bit [21:16]: Device 1 Cycle Time Count (R/W) - IDE0 Device 1 UDMA Cycle Time Count. This bit field is used for programming the UDMA Active and Recovery Time. * Bit [15:14]: Device 0 Data Input Delay (R/W) - IDE0 Device 0 Data Input Delay for UDMA Mode. This bit field is used for programming the data input delay in increments of 2 nsec in UDMA mode. * Bit [13:12]: Device 0 DSTROBE Delay (R/W) - IDE0 Device 0 DSTROBE Delay for UDMA Mode. This bit field is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode * Bit [11:09]: Device 0 HSTROBE Delay (R/W) - IDE0 Device 0 HSTROBE Delay for UDMA Mode. This bit field is used for programming the HSTROBE output delay in increments of 2 nsec in UDMA mode. * Bit [08:07]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [06]: Reserved (R/W) - This bit field is reserved. * Bit [05:00]: Device 0 Cycle Time Count (R/W) - IDE0 Device 0 UDMA Cycle Time Count. This bit field is used for programming the UDMA Active and Recovery Time (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 92 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.37 Test Register - IDE0 Address Offset: B0H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Module Select Nibble Select Sub-Module Select Data Field This register defines the test register for IDE Channel #0 in the SiI 0680A. This register is for chip-level simulation and verification purposes only. The register bits are defined below. * * * Bit [31:28]: Module Select (R/W) - IDE0 Test Module Select. This bit field is used to select the logic module for testing: 0001B = DIF module; 0010B = TMR module; 0011B = PIF module; and, 0100B = DUW module. Bit [27:24]: Nibble Select (R/W) - IDE0 Test Control Nibble Select. This bit field is used to select the control nibble for testing. A value of 0001B selects the least significant nibble, while a value of 1000B selects the most significant nibble. Bit [23:16]: Sub-Module Select (R/W) - IDE0 Test Sub-Module Select. This bit field is used to select the logic sub-module for testing. The valid selections are listed below. Module Select 0001B 0010B 0010B 0010B 0010B 0011B 0011B 0100B Sub-Module Select 0001B 0001B 0010B 0011B 0100B 0001B 0010B 0001B Description FIFO Data Timer 1 Timer 2 Timer 3 Timer 4 PBM_BYTE_CNT WD_TMO DUW_TMR_CNT Table 9-10: IDE0 Test Register Selections * Bit [15:00]: Data Field (R/W) - IDE0 Test Data Field. This bit field is used to write a preload value to the selected counter or read the current value of the selected counter. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 93 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.38 Data Transfer Mode - IDE0 Address Offset: B4H Access Type: Read/Write Reset Value: 0x0000_0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE0 Device 1 Transfer Mode Reserved Reserved IDE0 Device 0 Transfer Mode Reserved This register defines the transfer mode register for IDE Channel #0 in the SiI 0680A. The register bits are defined below. * * * Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [07:06]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [05:04]: Device 1 Transfer Mode (R/W) - IDE0 Device 1 Data Transfer Mode. This bit field is used to set the data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B = PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA. When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer. Bit [03:02]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [01:00]: Device 0 Transfer Mode (R/W) - IDE0 Device 0 Data Transfer Mode. This bit field is used to set the data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B = PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA. When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer. 9.7.39 IDE1 Task File Register 0 Address Offset: C0H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Task File Starting Sector Number IDE1 Task File Sector Count IDE1 Task File Features (W) IDE1 Task File Error (R) IDE1 Task File Data * * This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. Access to the individual bytes of this register is determined by the PCI bus Byte Enables at the time of the read or write operation. The register bits are defined below. * Bit [31:00]: IDE1 Task File Data (R/W). This bit field defines the IDE1 Task File Data register. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 0 must be active. To access 32-bit Task File Data, the Byte Enables for all four bytes must be active. Bit [31:24]: IDE1 Task File Starting Sector Number (R/W). This bit field defines the IDE1 Task File Starting Sector Number register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. Bit [23:16]: IDE1 Task File Sector Count (R/W). This bit field defines the IDE1 Task File Sector Count register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. Bit [15:08]: IDE1 Task File Features (W). This write-only bit field defines the IDE1 Task File Features register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. Bit [15:08]: IDE1 Task File Error (R). This read-only bit field defines the IDE1 Task File Error register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only. * * * * (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 94 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.40 IDE1 Task File Register 1 Address Offset: C4H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Task File Command + Status IDE1 Task File Device+Head IDE1 Task File Cylinder High IDE1 Task File Cylinder Low This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. Access to these bit fields is permitted if the PCI bus Byte Enable is active for one byte only. The register bits are defined below. * * * * * Bit [31:24]: register. Bit [31:24]: Bit [23:16]: register. Bit [15:08]: Bit [07:00]: IDE1 Task File Command (W). This write-only bit field defines the IDE1 Task File Command IDE1 Task File Status (R). This read-only bit field defines the IDE1 Task File Status register. IDE1 Task File Device+Head (R/W). This bit field defines the IDE1 Task File Device and Head IDE1 Task File Cylinder High (R/W). This bit field defines the IDE1 Task File Cylinder High register. IDE1 Task File Cylinder Low (R/W). This bit field defines the IDE1 Task File Cylinder Low register. 9.7.41 IDE1 Task File Register 2 Address Offset: C8H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved IDE1 Task File Device Control IDE1 Task File Auxiliary Status Reserved Reserved This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. Access to these bit fields is permitted if the PCI bus Byte Enable is active for one byte only. The register bits are defined below. * Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [23:16]: IDE1 Task File Device Control (W). This bit field defines the IDE1 Task File Device Control register. * Bit [23:16]: IDE1 Task File Auxiliary Status (R). This bit field defines the IDE1 Task File Auxiliary Status register. * Bit [15:00]: Reserved (R). This bit field is reserved and returns zeros on a read. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 95 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.42 IDE1 Read/Write Ahead Data Address Offset: CCH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Read Ahead Data This register defines the read ahead data port for PIO transfers on IDE Channel #1 in the SiI 0680A. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus byte enables. The data written to this register must be zero-aligned. 9.7.43 IDE1 Task File Register 0 - Command Buffering Address Offset: D0H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Task File Starting Sector Number IDE1 Task File Sector Count IDE1 Task File Features (W) IDE1 Task File Error (R) IDE1 Task File Data This register defines one of the IDE Channel #1 Task File registers used for Command Buffered accesses in the SiI 0680A. Access to the individual bytes of this register is determined by the PCI bus Byte Enables at the time of the read or write operation. The register bits are defined below. * Bit [31:00]: IDE1 Task File Data (R/W). This bit field defines the IDE1 Task File Data register. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus byte enables. The data written to this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 3 must be active. To access 32-bit Task File Data, the Byte Enables for all four bytes must be active. Bit [31:24]: IDE1 Task File Starting Sector Number (R/W). This bit field defines the IDE1 Task File Starting Sector Number register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 3 is active. Bit [23:16]: IDE1 Task File Sector Count (R/W). This bit field defines the IDE1 Task File Sector Count register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 2 is active. Bit [15:08]: IDE1 Task File Features (W). This write-only bit field defines the IDE1 Task File Features register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active. Bit [15:08]: IDE1 Task File Error (R). This read-only bit field defines the IDE1 Task File Error register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active. * * * * (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 96 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.44 IDE1 Task File Register 1 - Command Buffering Address Offset: D4H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Task File Command + Status IDE1 Task File Device+Head IDE1 Task File Cylinder High IDE1 Task File Cylinder Low This register defines one of the IDE Channel #1 Task File registers used for Command Buffered accesses in the SiI 0680A. The register bits are defined below. * * * * * Bit [31:24]: register. Bit [31:24]: Bit [23:16]: register. Bit [15:08]: Bit [07:00]: IDE1 Task File Command (W). This write-only bit field defines the IDE1 Task File Command IDE1 Task File Status (R). This read-only bit field defines the IDE1 Task File Status register. IDE1 Task File Device+Head (R/W). This bit field defines the IDE1 Task File Device and Head IDE1 Task File Cylinder High (R/W). This bit field defines the IDE1 Task File Cylinder High register. IDE1 Task File Cylinder Low (R/W). This bit field defines the IDE1 Task File Cylinder Low register. 9.7.45 Rserved Register Address Offset: D8H Access Type: Read Only Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Reserved * This bit field is reserved and returns an indeterminate value on a read. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 97 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.46 IDE1 Virtual DMA/PIO Read Ahead Byte Count Address Offset: DCH Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Virtual DMA/PIO Read Ahead Byte Count Not Used This register defines the read ahead byte count register for Virtual DMA and PIO Read Ahead transfers on IDE Channel #1 in the SiI 0680A. In Virtual DMA mode (PCI bus master DMA with PIO transfers on the IDE), all 32 bits are used as the wordaligned byte count. In PIO Read Ahead mode, only the lower 16 bits are used as the word-aligned byte count. The higher 16 bits must be programmed 0x0000. 9.7.47 IDE1 Task File Timing + Configuration + Status Address Offset: E0H Access Type: Read/Write Reset Value: 0x6515_0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Watchdog Timeout IORDY Monitoring Watchdog Int Ena Interrupt Status Virtual DMA Int Watchdog Ena Buffered Cmd Channel Rst Reserved Addr Setup Count Active Count Recovery Count Reserved Channel Tri-State This register defines the task file timing register for IDE Channel #1 in the SiI 0680A. See chapter 11 for details on programming this timing register. The register bits are defined below. * Bit [31:28]: Addr Setup Count (R/W) - IDE1 Address Setup Time Count. This bit field is used for programming the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N. * Bit [27:22]: Active Count (R/W) - IDE1 DIOR_N and DIOW_N Active Time Count. This bit field is used for programming the active time of IDE1_DIOR_N and IDE1_DIOW_N. * Bit [21:16]: Recovery Count (R/W) - IDE1 DIOR_N and DIOW_N Recovery Time Count. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N. * Bit [15]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [14] : Watchdog Int Ena ( R/W ) - IDE1 Watchdog Interrupt Enable. This bit is set to enable Interrupt when Watchdog timer expired. * Bit [13]: Watchdog Ena (R/W) - IDE1 Watchdog Timer Enable. This bit is set to enable the watchdog timer for IDE1. This bit is cleared to disable the watchdog timer. * Bit [12]: Watchdog Timeout (R) - IDE1 Watchdog Timer Timeout. This bit set indicates that the watchdog timer for IDE1 timed out. When enabled, and IORDY monitoring bit is also enabled, during IDE0 PIO opeartion, the watchdog counter starts counting when IORDY signal is deasserted. If after 256 PCI clocks cycles, the IORDY signal is still deasserted, the Watchdog Timer is expires, and this bit is set and the SiI 0680A continue its operation and stop monitoring IORDY signal. Software writes one to clear this bit. Once this bit is cleared, the SiI 0680A starts monitoring IORDY on channel 1 again. * Bit [11]: Interrupt Status (R) - IDE1 Interrupt Status. This bit set indicates that an interrupt is pending on IDE1. This bit provides real-time status of the IDE1 interrupt pin. * Bit [10]: Virtual DMA Int (R) - IDE1 Virtual DMA Completion Interrupt. This bit set indicates that the Virtual DMA data transfer has completed. This bit is cleared when bit[0] PBM enable in PCI Bus Master - IDE1 is cleared . * Bit [09]: IORDY Monitoring (R/W) - IDE1 IORDY Monitoring. When this bit is set, IORDY line is monitored for Task File accesses on channel 1. * Bit [08:04]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [03]: Channel Tri-State (R/W) - IDE1 Channel Tri-State. This bit is set to tri-state the IDE Channel #1 bus. This bit is cleared for normal operations. * Bit [02]: Channel Rst (R/W) - IDE1 Channel Reset. When this bit is set, IDE Channel # 1 RST signal is asserted. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 98 Cable 80 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. * * Bit [01]: Buffered Cmd (R) - IDE1 Buffered Command Active. This bit set indicates that a Buffered Command is currently active. This bit is set when the first command byte is written to the comand buffer. This bit is cleared when all of the task file bytes, including the command byte, have been written to the device. Bit [00]: Cable 80 (R) - IDE1 Cable 80 Detection. This bit provides real-time status of the inverted version of the IDE1_CBLID_N pin. When set, it indicates that 80 pin cable is detected. 9.7.48 IDE1 PIO Timing Address Offset: E4H Access Type: Read/Write Reset Value: 0x62DD_62DD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the PIO timing register for IDE Channel #1 in the SiI 0680A. See chapter 11 for details on programming this timing register. The register bits are defined below. * Bit [31:28]: Device 1 Addr Setup Count (R/W) - IDE1 Device 1 Address Setup Time Count for PIO Mode. This bit field is used for programming the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N in PIO mode. * Bit [27:22]: Device 1 Active Count (R/W) - IDE1 Device 1 DIOR_N and DIOW_N Active Time Count for PIO Mode. This bit field is used for programming the active time of IDE1_DIOR_N and IDE1_DIOW_N in PIO mode. * Bit [21:16]: Device 1 Recovery Count (R/W) - IDE1 Device 1 DIOR_N and DIOW_N Recovery Time Count for PIO Mode. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N in PIO mode. * Bit [15:12]: Device 0 Addr Setup Count (R/W) - IDE1 Device 0 Address Setup Time Count for PIO Mode. This bit field is used for programming the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N in PIO mode. * Bit [11:06]: Device 0 Active Count (R/W) - IDE1 Device 0 DIOR_N and DIOW_N Active Time Count for PIO Mode. This bit field is used for programming the active time of IDE1_DIOR_N and IDE1_DIOW_N in PIO mode. * Bit [05:00]: Device 0 Recovery Count (R/W) - IDE1 Device 0 DIOR_N and DIOW_N Recovery Time Count for PIO Mode. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N in PIO mode. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 99 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.49 IDE1 DMA Timing Address Offset: E8H Access Type: Read/Write Reset Value: 0x4392_4392 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Addr Setup Count Device 1 Active Count Device 1 Recovery Count Device 0 Addr Setup Count Device 0 Active Count Device 0 Recovery Count This register defines the DMA timing register for IDE Channel #1 in the SiI 0680A. See chapter 11 for details on programming this timing register. The register bits are defined below. * Bit [31:28]: Device 1 Addr Setup Count (R/W) - IDE1 Device 1 Address Setup Time Count for DMA Mode. This bit field is used for programming the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N in DMA mode. * Bit [27:22]: Device 1 Active Count (R/W) - IDE1 Device 1 DIOR_N and DIOW_N Active Time Count for DMA Mode. This bit field is used for programming the active time of IDE1_DIOR_N and IDE1_DIOW_N in DMA mode. * Bit [21:16]: Device 1 Recovery Count (R/W) - IDE1 Device 1 DIOR_N and DIOW_N Recovery Time Count for DMA Mode. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N in DMA mode. * Bit [15:12]: Device 0 Addr Setup Count (R/W) - IDE1 Device 0 Address Setup Time Count for DMA Mode. This bit field is used for programming the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N in DMA mode. * Bit [11:06]: Device 0 Active Count (R/W) - IDE1 Device 0 DIOR_N and DIOW_N Active Time Count for DMA Mode. This bit field is used for programming the active time of IDE1_DIOR_N and IDE1_DIOW_N in DMA mode. * Bit [05:00]: Device 0 Recovery Count (R/W) - IDE1 Device 0 DIOR_N and DIOW_N Recovery Time Count for DMA Mode. This bit field is used for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N in DMA mode. 9.7.50 IDE1 UDMA Timing Address Offset: ECH Access Type: Read/Write Reset Value: 0x4009_4009 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Device 1 Data Input Delay Device 0 Data Input Delay Device 1 DSTROBE Delay Device 1 HSTROBE Delay Device 0 DSTROBE Delay Reserved Reserved Device 1 Cycle Time Count Device 0 HSTROBE Delay Device 0 Cycle Time Count This register defines the UDMA timing register for IDE Channel #1 in the SiI 0680A. See chapter 11 for details on programming this timing register. The register bits are defined below. * Bit [31:30]: Device 1 Data Input Delay (R/W) - IDE1 Device 1 Data Input Delay for UDMA Mode. This bit field is used for programming the data input delay in increments of 2 nsec in UDMA mode. * Bit [29:28]: Device 1 DSTROBE Delay (R/W) - IDE1 Device 1 DSTROBE Delay for UDMA Mode. This bit field is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode. * Bit [27:25]: Device 1 HSTROBE Delay (R/W) - IDE1 Device 1 HSTROBE Delay for UDMA Mode. This bit field is used for programming the HSTROBE output delay in increments of 2 nsec in UDMA mode. * Bit [24:23]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [22]: Reserved (R/W) - This bit field is reserved. * Bit [21:16]: Device 1 Cycle Time Count (R/W) - IDE1 Device 1 UDMA Cycle Time Count. This bit field is used for programming the UDMA Active and Recovery Time. * Bit [15:14]: Device 0 Data Input Delay (R/W) - IDE1 Device 0 Data Input Delay for UDMA Mode. This bit field is used for programming the data input delay in increments of 2 nsec in UDMA mode. * Bit [13:12]: Device 0 DSTROBE Delay (R/W) - IDE1 Device 0 DSTROBE Delay for UDMA Mode. This bit field is used for programming the DSTROBE output delay in increments of 2 nsec in UDMA mode. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 100 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. * * * * Bit [11:09]: Device 0 HSTROBE Delay (R/W) - IDE1 Device 0 HSTROBE Delay for UDMA Mode. This bit field is used for programming the HSTROBE output delay in increments of 2 nsec in UDMA mode Bit [08:07]: Reserved (R). This bit field is reserved and returns zeros on a read. Bit [22]: Reserved (R/W) - This bit field is reserved. Bit [05:00]: Device 0 Cycle Time Count (R/W) - IDE1 Device 0 UDMA Cycle Time Count. This bit field is used for programming the UDMA Active and Recovery Time. 9.7.51 Test Register - IDE1 Address Offset: F0H Access Type: Read/Write Reset Value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Module Select Nibble Select Sub-Module Select Data Field This register defines the test register for IDE Channel #1 in the SiI 0680A. This register is for chip-level simulation and verification purposes only. The register bits are defined below. * Bit [31:28]: Module Select (R/W) - IDE1 Test Module Select. This bit field is used to select the logic module for testing: 0001B = DIF module; 0010B = TMR module; 0011B = PIF module; and, 0100B = DUW module. * Bit [27:24]: Nibble Select (R/W) - IDE1 Test Control Nibble Select. This bit field is used to select the control nibble for testing. A value of 0001B selects the least significant nibble, while a value of 1000B selects the most significant nibble. * Bit [23:16]: Sub-Module Select (R/W) - IDE1 Test Sub-Module Select. This bit field is used to select the logic sub-module for testing. The valid selections are listed below. Module Select 0001B 0010B 0010B 0010B 0010B 0011B 0011B 0100B Sub-Module Select 0001B 0001B 0010B 0011B 0100B 0001B 0010B 0001B Description FIFO Data Timer 1 Timer 2 Timer 3 Timer 4 PBM_BYTE_CNT WD_TMO DUW_TMR_CNT Table 9-11: IDE1 Test Register Selections * Bit [15:00]: Data Field (R/W) - IDE1 Test Data Field. This bit field is used to write a preload value to the selected counter or read the current value of the selected counter. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 101 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 9.7.52 Data Transfer Mode - IDE1 Address Offset: F4H Access Type: Read/Write Reset Value: 0x0000_0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IDE1 Device 1 Transfer Mode Reserved Reserved IDE1 Device 0 Transfer Mode Reserved This register defines the transfer mode register for IDE Channel #1 in the SiI 0680A. The register bits are defined below. * Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [07:06]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [05:04]: Device 1 Transfer Mode (R/W) - IDE1 Device 1 Data Transfer Mode. This bit field is used to set the data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B = PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA. When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer. * Bit [03:02]: Reserved (R). This bit field is reserved and returns zeros on a read. * Bit [01:00]: Device 0 Transfer Mode (R/W) - IDE0 Device 0 Data Transfer Mode. This bit field is used to set the data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B = PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA. When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 102 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 10. Design for Testability The SiI 0680A chip features internal scan for testability and fault coverage at the ASIC level, and a NAND tree for testability of the I/O pins at the board level. Test logic to support testing of the on-chip PLL is also included. Internal scan testing and PLL testing requires several bypass modes in the ASIC clocking system. These operational and bypass modes are illustrated in Fig. 10-1. JP Test Register SYS_NAND_TEST Nand Tree Normal Function 1 PCI_INTA_N 0 Normal Function 0 RST_PLL_TEST 4K & 1 MEM_CS_N PCI_IDSEL & SCAN_MODE BA5_EN & 1 PLL_TEST_CLK_SEL 33 MHz P_CLK 0 & 2 SYS_IDE_CLKSEL[1:0] PLL_TEST_MODE 2 3 TEST_MODE PCI_GNT_N ( FB Clock ) (Ref Clock) & 3 PLL 0 133 MHz 2 1 0 0 1 I0_CLK 100 MHz PCI_CLK (Test Clock) IDE0_DMARQ 2 2 5ns 0 1 I1_CLK 1 2 (Test Clock) PCI_CLK x 2 IDE0_CBLID_N IDE1_CBLID_N SCAN_EN (Test Clock) To all scan flip flops Figure 10-1: SiI 0680A Clocking System and Test Feature Diagram (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 103 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 10.1 Test Mode Register The test mode register selects the type of test to be performed and sets the I/O pins in the proper states. The test mode register in the SiI 0680A is programmed through the JP and TEST_MODE input pins. The test mode register is cleared by PCI reset. Table 10-1 lists the valid test mode settings. Register settings outside of those listed are ignored, and the chip operates in normal mode. 1 JP TEST_MODE 0 1 0 0 0 0 1 Figure 10-2: Test Mode Register Programming (A1H) Test Mode Register A0H A1H AAH Description Simulation test mode #0 Simulation test mode #1 NAND tree test mode Table 10-1: Test Mode Register Selections 10.2 NAND Tree Test The SiI 0680A features a NAND tree for parametric testing of the I/O pins. NAND tree testing allows the ASIC foundry to validate input voltage thresholds and wire bond connections. At the board level, the NAND tree provides connectivity checks between the PCB and package pins (signal pins only), in lieu of full JTAG boundary scan. When the SiI 0680A is programmed for NAND tree test mode, all outputs and bi-directional pins are set to input mode. A logic representation of the NAND tree is shown in Fig. 10-2. Refer to Table 10-2 for the NAND tree order. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 104 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. IDE0_DD00 IDE0_DD01 SCAN_EN MEM_CS_N NAND Test Mode Normal Function 0 1 PCI_INTA_N Figure 10-3: SiI 0680A NAND Tree Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name IDE0_DD00 IDE0_DD01 IDE0_DD02 IDE0_DD03 IDE0_DD04 IDE0_DD05 IDE0_DD06 IDE0_DD07 IDE0_DD08 IDE0_DD09 IDE0_DD10 IDE0_DD11 IDE0_DD12 IDE0_DD13 IDE0_DD14 IDE0_DD15 IDE0_CS0_N IDE0_CS1_N IDE0_DA0 IDE0_DA1 Order 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin Name IDE1_DD03 IDE1_DD04 IDE1_DD05 IDE1_DD06 IDE1_DD07 IDE1_DD08 IDE1_DD09 IDE1_DD10 IDE1_DD11 IDE1_DD12 IDE1_DD13 IDE1_DD14 IDE1_DD15 IDE1_CS0_N IDE1_CS1_N IDE1_DA0 IDE1_DA1 IDE1_DA2 IDE1_DIOR_N IDE1_DIOW_N Order 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin Name PCI_AD26 PCI_AD25 PCI_AD24 PCI_CBE3 PCI_IDSEL PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_CBE2 PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_DEVSEL_N PCI_STOP_N PCI_PERR_N Table 10-2: SiI 0680A NAND Tree Order (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 105 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 21 22 23 24 25 26 27 28 29 30 31 32 97 98 99 100 101 IDE0_DA2 IDE0_DIOR_N IDE0_DIOW_N IDE0_DMACK_N IDE0_CBLID_N IDE0_INTRQ IDE0_IORDY IDE0_DMARQ IDE0_RST_N IDE1_DD00 IDE1_DD01 IDE1_DD02 PCI_AD07 PCI_AD06 PCI_AD05 PCI_AD04 PCI_AD03 53 54 55 56 57 58 59 60 61 62 63 64 102 103 104 105 106 IDE1_CBLID_N IDE1_DMACK_N IDE1_INTRQ IDE1_IORDY IDE1_DMARQ IDE1_RST_N JP PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD02 PCI_AD01 PCI_AD00 PCI_REQ_N PCI_GNT_N 85 86 87 88 89 90 91 92 93 94 95 96 107 108 109 110 PCI_SERR_N PCI_PAR PCI_CBE1 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD09 PCI_AD08 PCI_CBE0 BA5_EN PCI_CLK SCAN_EN MEM_CS_N Table 10-2, SiI 0680A NAND Tree Order (continued) 10.3 Full Chip Internal Scan The SiI 0680A generates SCAN_MODE internal signal by asserting logic "1" on the following input pins TEST_MODE, BA5_EN, and PCI_GNT_N. The SCAN_MODE signal selects the source for the scan clocks and sets internal latches open during scan. The internal clocks for scan are provided as shown in Fig. 10-1, by the following pins: External Input Pins: PCI_CLK IDE0_CBLID IDE1_CBLID Internal Scan Clock: P_CLK I0_CLK I1_CLK Additionally, SCAN_EN selects between normal inputs and scan inputs at all the scan flip-flops is provided by the input pin SCAN_EN. There are six scan chains with input pins and output pins as follows: SCAN CHAIN SCAN INPUT PIN 1 IDE0_DMARQ 2 IDE0_INTRQ 3 IDE0_IORDY 4 IDE1_DMARQ 5 IDE1_INTRQ 6 IDE1_IORDY SCAN OUTPUT PIN PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 106 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 10.4 PLL TEST 10.4.1 BYPASSING the VCO The VCO in the analog phase-locked loop must be bypassed during digital logic simulation, to allow direct control of the PLL output clock. When PLL_CPBIAS is forced high the reference clock (PCI_CLK) is muxed to the PLL output. Automatic test equipment at the foundry also requires this test functionality to run the digital test vectors. 10.4.2 TESTING the VCO A divide-by-4K counter is used to measure the VCO frequency for any controlled voltage at the PLL_LOOPFLT pin. Normal Function 0 RST_PLL_TEST 4K & 1 MEM_CS_N PCI_IDSEL & SCAN_MODE BA5_EN & 1 PLL_TEST_CLK_SEL 33 MHz P_CLK 0 & 2 2 3 PLL_TEST_MODE TEST_MODE PCI_GNT_N ( FB Clock ) (Ref Clock) & PLL 0 1 PCI_CLK (Test Clock) IDE0_DMARQ PLL_CPBIAS Figure 10-4: PLL Test Logic (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 107 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 11. Programming Sequences 11.1 Recommended Initialization Sequence for the SiI 0680A The recommended initialization sequence for the SiI 0680A is detailed below. Initialize PCI Configuration Space registers * * * * * * * * Initialize Base Address Register 0 with the address of an 8-byte range in I/O space. Initialize Base Address Register 1 with the address of a 4-byte range in I/O space. Initialize Base Address Register 2 with the address of an 8-byte range in I/O space. Initialize Base Address Register 3 with the address of a 4-byte range in I/O space. Initialize Base Address Register 4 with the address of a 16-byte range in I/O space. Initialize Base Address Register 5 with the address of a 256-byte range in memory space. To enable the bios expansion ROM, initialize the Expansion ROM Base Address Register with the address of a 512KB range in memory space. Enable I/O space access, memory space access, and bus master operation by setting bits [2:0] of the PCI Command register. NOTE: The preceding configuration space register initialization is normally done by the motherboard BIOS in PC type systems. Set IDE clock frequency by programming bits [21:20] of the System Configuration Status and Command register at offset 88H in configuration space, or at base address 5, offset 48H. If the PCI-IDE arbiter's default FIFO read/write request thresholds are not suitable for the application they may be changed via the FIFO Valid Byte Count and Control IDEx register. The read threshold is defined by bits [05:00], and the write threshold is defined by bits [13:08] in the FIFO Valid Byte Count and Control - IDEx register. In most environments, setting these bit fields to zero results in the best utilization of the PCI bus by the 680A controller. If interrupt driven operation is not desired, set bits [23:22] of the System Configuration Status and Command register to block IDE interrupts from reaching the PCI bus. 11.2 ATA/ATAPI Device Initialization This section provides a general overview of the steps necessary to initialize an ATA/ATAPI device before it can be used for read/write operations. Select the ATA/ATAPI device. The device is selected by programming bits [23:16] in the IDEx Task File Register 1 register. If interrupt driven operation is desired, ensure that IDE interrupts are enabled by writing 0 to bits [23:16] of the IDEx Task File Register 2 register. For ATA devices only: Issue the Initialize Device Parameters command by * Programming bits [23:16] in the IDEx Task File 0 register with the number of logical sectors per logical track. * Programming bits [23:16] in the IDEx Task File 1 register with the maximum head number. * Programming bits [31:24] in the IDEx Task File Register 1 register with the value = 91H. * Wait for the command to complete. This can be accomplished by waiting for an interrupt if interrupts have been enabled at both the controller and the device. If interrupts are not (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 108 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. enabled, command completion can be detected by polling bits [31:24] of the IDEx Task File Register 1 register until the BUSY bit is no longer asserted. If device supports read/write multiple commands, issue the Set Multiple Mode command by: * Programming bits [23:16] in the IDEx Task File 0 register with the number of sectors per block to use on the following Read/Write Multiple commands. * Programming bits [31:24] in the IDEx Task File Register 1 register with the value = C6H. * Wait for the command to complete (see above). For both ATA and ATAPI devices: Set device transfer mode by: * Programming bits [15:08] in the IDEx Task File 0 register with the value 03H to "Set the transfer mode based on value in Sector Count Register". * Programming bits [23:16] in the IDEx Task File 0 register to the desired transfer mode. The settings are defined below: 08H = PIO Mode 0 09H = PIO Mode 1 0AH = PIO Mode 2 0BH = PIO Mode 3 0CH = PIO Mode 4 20H = Multiword DMA Mode 0 21H = Multiword DMA Mode 1 22H = Multiword DMA Mode 2 40H = Ultra DMA Mode 0 41H = Ultra DMA Mode 1 42H = Ultra DMA Mode 2 43H = Ultra DMA Mode 3 44H = Ultra DMA Mode 4 45H = Ultra DMA Mode 5 46H = Ultra DMA Mode 6 * * Programming bits [31:24] in the IDEx Task File Register 1 register with the value = EFH. Wait for the command to complete (see above). NOTE: An 80-pin cable is required to ensure signal quality can be maintained for transfer modes higher than Ultra DMA mode 2. When bit 0 of the IDEx Task File Timing + Configuration + Status register is set, an 80-pin cable may be present (see the ATA/ATAPI specification for details on how this bit should be interpreted). 11.3 Initialization of Controller Channel Timing Registers There are four types of timing registers associated with a channel. The IDEx Task File Timing + Configuration + Status register controls the timing of ATA/ATAPI device task file register accesses (except for accesses to the data register). Since this register controls the task file access timing for all devices attached to the channel, it is important to program this register with values that do not exceed the capabilities of the slowest device attached to the channel. The IDEx PIO Timing register controls the access timing of the task file data register when programmed I/O is used to transfer data to or from the device. The IDEx DMA Timing register controls the data transfer timing when the device and controller have been setup to use a multiword DMA transfer mode. The IDEx UDMA Timing register controls the data transfer timing when the device and controller have been setup to use an Ultra DMA transfer mode. Data transfer timing can be set independently for each device. The following steps need to be performed to configure the controller timing to match the transfer mode selected for the ATA/ATAPI device: Set the task file register access timing. The task file register timing is set by programming bits [31:16] of the IDEx Task File Timing + Configuration + Status register. See section 13.2.1 for recommended values to (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 109 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. program into this register for each PIO mode. If there is more than one device attached to the channel, select the PIO mode of the slowest device. If PIO mode 3 or 4 is selected, bit 9 of the IDEx Task File Timing + Configuration + Status register must also be set to enable the controller to monitor the state of the IORDY signal. Set the PIO data transfer timing. The PIO data transfer timing is set by programming bits [15:0] for device 0, or bits [31:16] for device 1, of the IDEx PIO Timing register. See section 13.2.2 for recommended values to program into this register for each PIO mode. The default value of this register sets the timing slow enough to work with any ATA/ATAPI device, so this step is optional if the ATA/ATAPI device will not be used in PIO mode. Set the multiword DMA data transfer timing. This step is necessary only if the ATA/ATAPI device will be operated in a multiword DMA mode. The multiword DMA timing is set by programming bits [15:0] for device 0, or bits [31:16] for device 1, of the IDEx DMA Timing register. See section 13.2.3 for recommended values to program into this register for each multiword DMA mode. Set the Ultra DMA data transfer timing. This step is necessary only if the ATA/ATAPI device will be operated in an Ultra DMA mode. The Ultra DMA timing is set by programming bits [15:0] for device 0, or bits [31:16] for device 1, of the IDEx UDMA Timing register. See sections 13.2.4 and 13.2.5 for recommended values to program into this register for each Ultra DMA mode. In order to use the controller's DMA capability to perform the data transfer for an ATA/ATAPI command, the controller needs to be configured for the transfer mode to use when transferring data to or from the ATA bus. The data transfer mode is set by programming bits [1:0] for device 0, or bits [5:4] for device 1, of the IDEx Data Transfer Mode register. The transfer mode select values are listed below: 00B = PIO Mode without IORDY monitoring 01B = PIO Mode with IORDY monitoring 10B = Multiword DMA 11B = Ultra DMA NOTE: When using PIO to perform a data transfer, this register only instructs the controller as to whether or not it should monitor the IORDY signal when the task file data register is accessed. Any value other than 00H will cause the controller to monitor the IORDY signal. 11.4 Issue ATA Command The following describes the sequence to issue a read/write type command to an ATA device. Select the IDE device. The IDE device is selected by programming bits [23:16] in the IDEx Task File Register 1 register. Set the number of sectors to be transferred by programming bits [23:16] of the IDEx Task File Register 0 register. Set the location of data to be transferred. The location is defined by programming the following. Bits [31:24] in the IDEx Task File Register 0 register define the Starting Sector. Bits [23:16] in the IDEx Task File Register 1 register define the Device and Head value. Bits [15:08] in the IDEx Task File Register 1 register define the Cylinder High value. Bits [07:00] in the IDEx Task File Register 1 register define the Cylinder Low value. Issue the Read/Write PIO/DMA command by programming bits [31:24] in the IDEx Task File Register 1 register with the command desired. 11.5 IDE PIO Mode Read/Write Operation Once the SiI 0680A is initialized via the initialization sequence described in Section 11.1, the ATA device has been initialized for PIO mode data transfer per the guidelines in section 11.2, and the controller channel has been initialized for PIO mode data transfer per the instructions in section 11.3, PIO read/write operations may be performed by following the programming sequence described below. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 110 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Issue a PIO Read/Write command to device following the steps in section 11.4. Read Operation Wait until an IDE channel interrupt (bit 11 in the IDEx Task File Timing + Configuration + Status register is set). Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt and determine if there was error. If no error, continue to read IDE data via the IDEx Task File Register 0 register, until the expected number of sectors of data per interrupt are read. Repeat the above three steps until all data for the read command has been transferred or an error has been detected. Write Operation Wait until bit 27(DRQ) in the IDEx Task File Register 1 register is set. Continue to write IDE data via the IDEx Task File Register 0 register until the expected number of sectors of data per interrupt are written. Wait until an IDE channel interrupt (bit 11 in the IDEx Task File Timing + Configuration + Status register is set). Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt and determine if there was error. If no error, repeat the previous four steps until all data for the write command has been transferred or an error has been detected. 11.6 Watchdog Timer Operation The purpose of the watchdog timer is to prevent the host system from hanging because a device operating in PIO mode stopped responding to task file accesses. In PIO modes 0, 1, and 2, device access is completely controlled by the values programmed into the Task File Timing and PIO Timing registers. In these modes it is not possible for a non-responsive device to hang-up the host system. However, in PIO modes 3 and 4, device task file accesses are not regulated by the timing registers alone, but can also be controlled by the device through the use of the IORDY signal. If, during a task file access by the host, the device negates IORDY and then stops responding, the host will hang waiting for the access to complete. It is this type of hang, that the watchdog timer is designed to protect against. The watchdog timer monitors the length of time the IORDY signal is negated. If the watchdog timer detects that the the IORDY signal has remained negated longer than the watchdog timeout period (approximately 7.75us), the watchdog timer will force the task file access cycle to complete, and set the watchdog timeout bit in the IDEx Task File Timing + Configuration + Status register. The data associated with a timed out access should be considered invalid. Additionally, the watchdog timer can be configured to generate an interrupt when a timeout is detected by setting bit 14 of the IDEx Task File Timing + Configuration + Status register. The watchdog timer feature is disabled by default. In addition to the controller channel initialization specified in section 11.3, add the following two steps to enable the watchdog timer: Enable the watchdog timer by setting bit 13 of the IDEx Task File Timing + Config + Status register. If an interrupt is desired whenever the watchdog times out, enable the watchdog interrupt by setting bit 14 of the IDEx Task File Timing + Config + Status register. The following programming sequences are needed for each PIO Mode 3 or 4 Read/Write Operation with the watchdog timer enabled: Issue a Read/Write PIO Command to the ATA drive following the steps in section 11.4. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 111 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Read Operation Wait for an IDE channel interrupt. If controller interrupts are disabled, poll for the IDE interrupt by reading the IDEx Task File Timing + Configuration + Status register. If bit 12 is set, a watchdog timeout has occurred. If bit 11 is set, the ATA device is interrupting. If the watchdog timeout bit is set, Write 1 to bit 12 in the IDEx Task File Timing + Configuration + Status register to clear watchdog timeout status. The watchdog timeout represents a fatal error as far as the current ATA command is concerned. A course of action that might be appropriate at this point might be to reset and reinitialize the ATA channel and then retrying the command that failed. If the ATA device interrupt bit is set, Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt and determine if there was an error. Write 1 to bit 18 of the PCI Bus Master - IDEx Register to i clear the latched interrupt status. Note that clearing the PCI interrupt does not clear bit 18 as this bit needs to be cleared separately. If the ATA device is not reporting an error, continue to read IDE data via the IDEx Task File Register 0 register, until the expected number of sectors of data per interrupt are read. Repeat the read operation steps until all data for the read command has been transferred or an error has been detected. Write Operation Wait until bit 27(DRQ) in the IDEx Task File Register 1 register is set. Continue to write IDE data via the IDEx Task File Register 0 register until the expected number of sectors of data per interrupt are written. Wait for an IDE channel interrupt. If controller interrupts are disabled, poll for the IDE interrupt by reading the IDEx Task File Timing + Configuration + Status register. If bit 12 is set, a watchdog timeout has occurred. If bit 11 is set, the ATA device is interrupting. If the watchdog timeout bit is set, Write 1 to bit 12 in the IDEx Task File Timing + Configuration + Status register to clear watchdog timeout status. The watchdog timeout represents a fatal error as far as the current ATA command is concerned. A course of action that might be appropriate at this point might be to reset and reinitialize the ATA channel and then retrying the command that failed. If the ATA device interrupt bit is set, Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt and determine if there was an error. Write 1 to bit 18 of the PCI Bus Master - IDEx Register to clear the ATA interrupt. If no error, repeat the write operation steps until all data for the write command has been transferred or an error has been detected. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 112 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 11.7 IDE PIO Mode Read Ahead Operation Read ahead operation allows the controller to "pre-fetch" data from the IDE bus and store it in the controller's channel fifo, where it will later be retrieved by the host. This mode of operation has the potential to speed-up PIO data transfers by not forcing the host to wait the programmed PIO cycle time for every access to the task file data register. The amount of any speed increase will depend on the PIO mode in use, the characteristics of the host PCI bus, as well as the speed of the host processor. To use the controller's PIO read ahead capability, make the following changes to the "Read Operation" portion of sections 11.5 and 11.6. Just prior to retrieving the read data, set the read ahead byte count by programming bits [15:00] in the IDEx Virtual DMA/PIO Read Ahead Byte Count register with the exact number of bytes to be read for the interrupt. Instead of reading the IDEx Task File Register 0 register to retrieve the data, read the IDEx Read Ahead Data register instead. 11.8 IDE MDMA/UDMA Read/Write Operation Once the SiI 0680A is initialized via the initialization sequence described in Section 11.1, the ATA device has been initialized for MDMA/UDMA mode data transfer per the guidelines in section 11.2, and the controller channel has been initialized for MDMA/UDMA mode data transfer per the instructions in section 11.3, DMA read/write operations may be performed by following the programming sequence described below. Issue a DMA read/write command to the device following steps in section 11.4. Program Bus Master Registers Clear bit 17 in the PCI Bus Master - IDEx register. This bit is set if an error occurred during the previous DMA access. Clear bit 18 in the PCI Bus Master - IDEx register. This bit is set if an IDE interrupt occurred during the previous DMA access. Create a Physical Region Descriptor (PRD) Table. A PRD table is an array where each entry describes the location and size of a physical memory buffer that will be used during the DMA operation. Each PRD table entry is 64-bits in length, formatted as follows; bits [31:0] contain the 32-bit starting address of the memory buffer, bits [47:32] contain the 16-bit size of the memory buffer, bits [62:48] are normally unused (see section 11.10 for details of how these bits may be used), bit 63 flags the end of the PRD table and therefore should only be set in the last entry of the PRD table. The PRD table itself must be constructed in a memory region that can be directly accessed by the 680A controller. Once the PRD table is built, the controller must be informed of its location. This is accomplished by writing the 32-bit address of the PRD table to the PRD Table Address - IDEx register. Enable DMA transfer. DMA is enabled by writing bits [7:0] of the PCI Bus Master - IDEx register. Bit 3 of this register controls the direction of the DMA transfer; 1 = write to memory, 0 = read from memory. Setting bit 0 of the register enables the controller to perform DMA operations. Note: Task file registers are inaccessible as long as bit 0 is set. Wait for a PCI interrupt. When a PCI interrupt occurs, read the PCI Master - IDEx status register and check the DMA status bits. The possible combinations of the status bits [18:16] are defined below. 000B = If the IDE device does not report an error, then the PRD table specified a size that is smaller than the IDE transfer size. 001B = DMA transfer in progress. 010B = The controller had a problem transferring data to/from memory. 100B = Normal completion. 101B = If the IDE device does not report an error, then the PRD specified a size that is larger than the IDE transfer size. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 113 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Make sure PCI bus master operation of the SiI 0680A is stopped by clearing bit 0 of the PCI Bus Master - IDEx register. Note: The task file registers are not accessible as long as bit 0 is set. Clearing bit 0 causes bit 16 to be cleared as well. Read the device status at bits [13:24] in the IDEx Task File Register 1 register to clear the device interrupt and determine if there was error. Write `1' to bit 18 (write-one-to-clear) in the PCI Bus Master - IDEx register to clear the PCI Interrupt. 11.9 IDE Virtual DMA Read/Write Operation In virtual DMA operation the controller uses a PIO data transfer mode to move data between an ATA/ATAPI device and the controller, and uses DMA to move that same data between the controller and the host memory. For ATA/ATAPI devices that cannot operate in a "true" DMA mode, virtual DMA provides two benefits; first, using DMA to move data reduces the demand on the host CPU, and second, systems that use virtual memory often require that data buffers that will be accessed directly by low level device drivers be "mapped" into the operating system's address space, in virtual DMA mode the CPU does not access the data buffer directly, so the overhead of obtaining the mapping to operating system address space is eliminated. 11.9.1 Using Virtual DMA with Non-DMA Capable Devices Once the SiI 0680A is initialized via the initialization sequence described in Section 11.1, the ATA device has been initialized for PIO mode data transfer per the guidelines in section 11.2, and the controller channel has been initialized for PIO mode data transfer per the instructions in section 11.3, virtual DMA read/write operations may be performed by following the programming sequence described below. NOTE: The watchdog timer feature is compatible with virtual DMA operation. See section 11.7 for details about using the watchdog timer. Issue a PIO read/write command to the device following steps in section 11.4. Read Operation Wait for a PCI interrupt. Read the DMA status bits [18:16] of the PCI Bus Master - IDEx register, and check that bit 18 is set to make sure the interrupt was generated by the expected channel. If expected channel interrupted, read bits [11:10] of the channel's IDEx Task File Timing + Configuration + Status register to determine the cause of the interrupt. Bit 11 is set if the ATA/ATAPI device has an interrupt pending, bit 10 is set if a virtual DMA operation completed. If a virtual DMA operation completed, Write 00H to bits [7:0] of the PCI Bus Master - IDEx register to disable DMA operation. Write 1 to bits [18:17] of the PCI Bus Master -IDEx register to reset the DMA status and virtual DMA interrupt bits, and the PCI interrupt. Check the previously read DMA status bits to ensure the DMA completed successfully. See section 11.8 for more information about interpreting the DMA status bits. Because ATA/ATAPI commands that transfer data using PIO can generate several interrupts during the data transfer phase of the command, a race condition is created between the interrupt indicating the completion of a virtual DMA operation, and the interrupt from the ATA/ATAPI device indicating it is ready to perform the next part of the data transfer. To prevent missing an ATA/ATAPI device interrupt due to this race condition, it is necessary to re-read the channel's IDEx Task File Timing + Configuration + Status register after disabling DMA operation and examining bit (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 114 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 11. If bit 11 is set, the ATA/ATAPI device is interrupting and should be serviced by following the steps below (assuming that the virtual DMA operation completed successfully). If the ATA/ATAPI device has interrupted, Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt and determine if there was an error. Write 1 to bit 18 of the PCI Bus Master - IDEx register to clear the DMA Complete bit (NOTE: The DMA Complete bit acts as a latched copy of the ATA interrupt line when the channel is not performing a DMA operation). If the ATA/ATAPI device is not reporting an error, and DRQ is asserted (bit 27 of IDEx Task File Register 1), then the device is interrupting to transfer data to the host. To transfer the data, the DMA registers are setup to only perform that part of the data transfer expected for this interrupt. The DMA is setup similarly to the way it is when performing a normal read DMA command, but with one additional step. Before the DMA is enabled, the IDEx Virtual DMA/PIO Read Ahead Byte Count register must be written with the 32-bit count of the number of bytes to be transferred for this interrupt. Repeat the above steps until all data for the read command has been transferred or an error has been detected. Write Operation Poll the IDEx Task File Register 1 bits [31:24] until either bit 27 (DRQ) is set indicating the device is ready for write data transfer, or bit 24 (ERR) is set indicating the device has detected an error with the write command. If no error, and DRQ is asserted (bit 27 of IDEx Task File Register 1), then the device is waiting for write data transfer. To transfer the data, the DMA registers are setup to only perform that part of the data transfer expected at this time. For example, a Write Sectors command would expect to transfer 1 sector (512 bytes), while a Write Multiple command would expect to transfer the lesser of the number of sectors set by the Set Multiple Mode command or the total number of sectors specified by the Write Multiple command. The DMA is setup similarly to the way it is when performing a normal write DMA command, but with one additional step. Before the DMA is enabled, the IDEx Virtual DMA/PIO Read Ahead Byte Count register must be written with the 32-bit count of the number of bytes to be transferred. Wait for a PCI interrupt. Read the DMA status bits [18:16] of the PCI Bus Master - IDEx register, and check that bit 18 is set to make sure the interrupt was generated by the expected channel. If expected channel interrupted, read bits [11:10] of the channel's IDEx Task File Timing + Configuration + Status register to determine the cause of the interrupt. Bit 11 is set if the ATA/ATAPI device has an interrupt pending, bit 10 is set if a virtual DMA operation completed. If a virtual DMA operation completed, Write 00H to bits [7:0] of the PCI Bus Master - IDEx register to disable DMA operation. Write 1 to bits [18:17] of the PCI Bus Master -IDEx register to reset the DMA status and virtual DMA interrupt bits, and PCI interrupt. Check the previously read DMA status bits to ensure the DMA completed successfully. See section 11.8 for more information about interpreting the DMA status bits. Because ATA/ATAPI commands that transfer data using PIO can generate several interrupts during the data transfer phase of the command, a race condition is created between the interrupt indicating the completion of a virtual DMA operation, and the interrupt from the ATA/ATAPI device indicating it is ready to perform the next part of the data transfer. To prevent missing an ATA/ATAPI device interrupt due to this race condition, it is necessary to re-read the channel's IDEx Task File Timing + Configuration + Status register after disabling DMA operation and examining bit 11. If bit 11 is set, the ATA/ATAPI device is interrupting and should be serviced by following the steps below (assuming that the virtual DMA operation completed successfully). (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 115 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. If the ATA/ATAPI device has interrupted, Read the device status at bits [31:24] in the IDEx Task File Register 1 register to clear the device interrupt and determine if there was an error. Write 1 to bit 18 of the PCI Bus Master - IDEx register to clear the DMA Complete bit (NOTE: The DMA Complete bit acts as a latched copy of the ATA interrupt line when the channel is not performing a DMA operation). If the ATA/ATAPI device is not reporting an error, and DRQ is asserted (bit 27 of IDEx Task File Register 1), then the device is interrupting to transfer data to the device. To transfer the data, the DMA registers are setup to only perform that part of the data transfer expected for this interrupt. The DMA is setup similarly to the way it is when performing a normal write DMA command, but with one additional step. Before the DMA is enabled, the IDEx Virtual DMA/PIO Read Ahead Byte Count register must be written with the 32-bit count of the number of bytes to be transferred for this interrupt. Repeat the above steps starting at "Wait for PCI interrupt" until all data for the write command has been transferred or an error has been detected. 11.9.2 Using Virtual DMA with DMA Capable Devices Even though a device may be DMA capable, there are ATA/ATAPI commands that require that a PIO mode be used to transfer data. For these commands, virtual DMA can be used to perform the data transfer. Using virtual DMA with an ATA/ATAPI device that has already been configured to use DMA for normal read/write operation is performed very much like the sequence described above for PIO mode only devices, but with the following additional considerations: * The Data Transfer Mode - IDEx register associated with the ATA/ATAPI device needs to be programmed for a PIO type transfer mode before DMA operation is enabled, and must be reprogrammed with the DMA/UDMA transfer type used during normal DMA operation once the virtual DMA operation is complete. A PIO mode compatible with the device should be programmed into the appropriate IDEx - PIO Timing register. This register does not have to be written for every command that uses virtual DMA, instead it should be written as part of the controller initialization sequence. * 11.10 Second PCI Bus Master Registers Usage In order to provide backward compatibility with existing drivers, the Physical Region Descriptor (PRD) tables used by the 680A controller when performing DMA transfers suffer the following limitations; a PRD table entry cannot represent a memory area greater than 64k, nor can a PRD table entry represent a memory area that spans a 64k address boundary. Whenever DMA is initiated via the PCI Bus Master - IDEx registers, the foregoing limitations are enforced by the 680A controller. A feature known as Large Block Transfer has been added to the SiI 0680A controller to allow new drivers to get around the 64k size and address limits of PRD table entries expected by existing drivers. Large Block Transfer simplifies the creation of PRD tables by reducing the number of table entries that need to be created and eliminating the need to make sure a memory region does not cross a 64k boundary. Large Block Transfer mode is enabled whenever DMA is initiated by writing to the PCI Bus Master 2 - IDEx registers (base address 5, offset 10H or 18H). When performing DMA in Large Block Transfer mode, the 680A controller interprets the fields of a PRD table entry differently. In all other respects, DMA interrupt generation, DMA status bit interpretation, etc..., Large Block Transfer mode behaves identically to a non-Large Block Transfer mode DMA operation. The following table describes the format of a PRD table entry: Bits 31:0 Bits 47:32 32-bit starting address of the memory region. When not operating in Large Block Transfer mode, this field specifies the size of the memory region. If the size of the memory region is greater than 64k, or crosses a 64k address boundary, then two or more PRD table entries will need to be created to describe it. If operating in Large Block Transfer mode, this field contains the least significant 16-bits of the size of the memory region. If not operating in Large Block Transfer mode, this field is unused. SiI-DS-0069-C 116 Bits 62:48 (c) 2006 Silicon Image, Inc. SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. If operating in Large Block Transfer mode, this field contains the most significant 15-bits of the size of the memory region. When set, this bit indicates that this is the last entry in the PRD table. Table 11-1, Physical Region Descriptor (PRD) Format Bit 63 (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 117 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 12. FLASH and EEPROM Programming Sequences 12.1 FLASH Memory Access The SiI 0680A supports an external FLASH memory device up to 4 Mbits in capacity. Access to the FLASH memory is available through two means: PCI Direct Access and Register Access. 12.1.1 PCI Direct Access Access to the Expansion Rom is enabled by setting bit 0 in the Expansion Rom Base Address register at Offset 30h of the PCI Configuration Space. When this bit is set, bits [31:19] of the same register are programmable by the system to set the base address for all FLASH memory accesses. Read and write operations with the FLASH memory are initiated by Memory Read and Memory Write commands on the PCI bus. Accesses may be as Bytes, Words, or DWords. 12.2.2 Register Access This type of FLASH memory access is carried out through a sequence of internal register read and write operations. The proper programming sequences are detailed below. FLASH Write Operation Verify that bit 25 is cleared in the register at Offset 50H of Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete and ready for another operation. Program the write address for the FLASH memory access. The address field is defined by bits [18:00] in the FLASH Memory Address - Command + Status register. Program the write data for the FLASH memory access. The data field is defined by bits [07:00] in the FLASH Memory Data register at Offset 54 of Base Address 5. Program the memory access type . The memory access type is defined by bit 24 in the FLASH Memory Address - Command + Status register. The bit must be cleared for a memory write access. Initiate the FLASH memory access by setting bit 25 in the FLASH Memory Address - Command + Status register. FLASH Read Operation Verify that bit 25 is cleared in the FLASH Memory Address - Command + Status register at Offset 50H of Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete and ready for another operation. Program the read address for the FLASH memory access. The address field is defined by bits [18:00] in the FLASH Memory Address - Command + Status register. Program the memory access type. The memory access type is defined by bit 24 in the FLASH Memory Address - Command + Status register. The bit must be set for a memory read access. Initiate the FLASH memory access by setting bit 25 in the FLASH Memory Address - Command + Status register. Verify that bit 25 is cleared in the FLASH Memory Address - Command + Status register. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete. Read the data from the FLASH memory access. The data field is defined by bits [07:00] in the FLASH Memory Data register at Offset 54H of Base Address 5. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 118 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 12.2 EEPROM Memory Access The SiI 0680A supports an external 256-byte EEPROM memory device. Access to the EEPROM memory is available through internal register operations in the SiI 0680A. EEPROM Write Operation Verify that bit 25 is cleared in the EEPROM Memory Address - Command + Status register at Offset 58H of Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete and ready for another operation. Write `1' to clear bit 28 in the EEPROM Memory Address - Command + Status register. The bit is set if an error occurred during a previous memory access. Program the write address for the EEPROM memory access. The address field is defined by bits [07:00] in the EEPROM Memory Address - Command + Status register. Program bits [15:08] to zero. Program the write data for the EEPROM memory access. The data field is defined by bits [07:00] in the EEPROM Memory Data register at Offset 5CH of Base Address 5. Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory Address - Command + Status register. The bit must be cleared for a memory write access. Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address - Command + Status register. Poll bit 25 in the EEPROM Memory Address - Command + Status register. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete. Check bit 28 in the EEPROM Memory Address - Command + Status register. The bit is set if an error occurred during a previous memory access. EEPROM Read Operation Verify that bit 25 is cleared in the EEPROM Memory Address - Command + Status register at Offset 58H of Base Address 5. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete and ready for another operation. Write `1' to clear bit 28 in the EEPROM Memory Address - Command + Status register. The bit is set if an error occurred during a previous memory access. Program the read address for the EEPROM memory access. The address field is defined by bits [07:00] in the EEPROM Memory Address - Command + Status register. Program bits [15:08] to zero. Program the memory access type. The memory access type is defined by bit 24 in the EEPROM Memory Address - Command + Status register. The bit must be set for a memory read access. Initiate the EEPROM memory access by setting bit 25 in the EEPROM Memory Address - Command + Status register. Poll bit 25 in the EEPROM Memory Address - Command + Status register. The bit reads one when a memory access is currently in progress. It reads zero when the memory access is complete. Check bit 28 in the EEPROM Memory Address - Command + Status register. The bit is set if an error occurred during a previous memory access. Read the data from the EEPROM memory access. The data field is defined by bits [07:00] in the EEPROM Memory Data register at Offset 5CH of Base Address 5. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 119 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 13. SiI 0680A Timing Registers 13.1 Timing Register Definition RECOVERY COUNT TIMING Bits [21:16] IDE0 Task File Timing + Configuration + Status Bits [05:00] IDE0 PIO Timing Bits [21:06] IDE0 PIO Timing Bits [05:00] IDE1 PIO Timing Bits [21:06] IDE1 PIO Timing ACTIVE COUNT TIMING Bits [27:22] IDE0 Task File Timing + Configuration + Status Bits [11:06] IDE0 PIO Timing Bits [27:22] IDE0 PIO Timing Bits [11:06] IDE1 PIO Timing Bits [27:22] IDE1 PIO Timing Value 00h 01h 02h 03h ... 3Fh 1 1 2 3 Active Time in PCI Clock 63 ADDRESS SETUP COUNT TIMING Bits [31:28] IDE0 Task File Timing + Configuration + Status Bits [15:12] IDE0 PIO Timing Bits [31:28] IDE0 PIO Timing Bits [15:12] IDE1 PIO Timing Bits [31:28] IDE1 PIO Timing Value 0h 1h 2h 3h UDMA Cycle Time Count Timing Value 00h 01h 02h 03h ... 3Fh 2 2 3 4 1 1 2 3 Active Time in PCI Clock Cycle Time in IDE Clock 64 In the UDMA timing register. the number of clocks is always 1 greater than the value loaded for the cycle time count. The only exception is that value "0" requires two cycles. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 120 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 13.2 Timing Registers Programming Suggestion 13.2.1 TF Timing Register Programming in Number of 33 MHz PCI clock TF 0 3 10 10 328Ah TF 1 2 10 3 2283h TF 2 1 10 1 1281h TF 3 1 3 3 10C3h TF 4 1 3 1 10C1h Address Setup Active Count Recovery Count TF Timing Register 13.2.2 PIO Timing Register Programming in Number of 33 MHz PCI clock PIO 0 3 10 10 328Ah PIO 1 2 10 3 2283h PIO 2 1 4 4 1104h PIO 3 1 3 3 10C3h PIO 4 1 3 1 10C1h Address Setup Active Count Recovery Count PIO Timing Register 13.2.3 DMA Timing Register Programming in Number of 33 MHz PCI clock MDMA 0 2 8 8 2208h MDMA 1 1 3 2 10C2h MDMA 2 1 3 1 10C1h Address Setup Active Count Recovery Count PIO Timing Register 13.2.4 UDMA Timing Register Programming in Number of 100 MHz IDE clock Cycle UDMA 0 11 UDMA 1 7 UDMA 2 5 UDMA 3 4 UDMA 4 2 UDMA 5 1 13.2.4 UDMA Timing Register Programming in Number of 133 MHz IDE clock UDMA 0 15 UDMA 1 11 UDMA 2 7 UDMA 3 5 UDMA 4 3 UDMA 5 2 UDMA 6 1 Cycle (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 121 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. 14. Errata The 680A returns Target Abort when CBE#[3:0] = 1111 When an access is made to the 680A memory region with Data Byte Enable = 0FH (no data to be transferred) and the address is within the 680A Delay-Transaction Region, instead of terminating the transaction normally, terminates the transaction with Target Abort. This does not comply with the PCI specification and may result in system errors in some systems. This may happen when the 680A is on a 64-bit PCI bus and the host issues a 64-bit transaction with only low or high Dword bytes enabled. Since 680A only supports 32-bit transactions, the host may break the 64-bit transaction into two 32-bit transactions in which, one of the transactions is a dummy transaction with all Byte Enables set to 1111. The Delay-Transaction Region on the 680A includes: the FIFO region (BA5 + (60h-7Fh)); the IDE0 Task File Region (BA5 + (80h-8Fh)); and the IDE1 Task File Region (BA5 + (C0h-CFh)). Impact: May result in system errors in some systems. Workaround: At present this has only been observed in an environment in which conditions have been forced with a PCI bridge device. No tested motherboards have experienced problems. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 122 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Legal Statement Copyright Notice Copyright (c) 2006 Silicon Image, Inc. All rights reserved. These materials contain proprietary and/or confidential information (including trade secrets, copyright and/or other interests) of Silicon Image, Inc. You may not use these materials except only for your bona fide non-commercial evaluation of your potential purchase of products and/services from Silicon Image or its affiliates, and/or only in connection with your purchase of products and/or services from Silicon Image or its affiliates, and only in accordance with the terms and conditions herein. You have no right to copy, modify, transfer, sublicense, publicly display, create derivative works of or distribute these materials, or otherwise make these materials available, in whole or in part, to any third party. Trademark Acknowledgment Silicon ImageTM, VastLaneTM, SteelVineTM, PinnaClearTM, SimplayTM, Simplay HDTM, SatalinkTM, and TMDSTM are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other countries. HDMITM, the HDMI logo and HighDefinition Multimedia InterfaceTM are trademarks or registered trademarks of, and are used under license from, HDMI Licensing, LLC. Disclaimers These materials are provided on an "AS IS" basis. SILICON IMAGE, INC. AND ITS AFFILIATES DISCLAIM ALL REPRESENTATIONS AND WARRANTIES (EXPRESS, IMPLIED, STATUTORY OR OTHERWISE), INCLUDING BUT NOT LIMITED TO: (I) ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND/OR NON-INFRINGEMENT OF THIRD PARTY RIGHTS; (II) ALL WARRANTIES ARISING OUT OF COURSE-OFDEALING, USAGE, AND/OR TRADE; AND (III) ALL WARRANTIES THAT THE INFORMATION OR RESULTS PROVIDED IN, OR THAT MAY BE OBTAINED FROM USE OF, THE MATERIALS ARE ACCURATE, RELIABLE, COMPLETE, UP-TODATE, OR PRODUCE SPECIFIC OUTCOMES. SILICON IMAGE, INC. AND ITS AFFILIATES ASSUME NO LIABILITY OR RESPONSIBILITY FOR ANY ERRORS OR OMISSIONS IN THESE MATERIALS, MAKES NO COMMITMENT OR WARRANTY TO CORRECT ANY SUCH ERRORS OR OMISSIONS OR UPDATE OR KEEP CURRENT THE INFORMATION CONTAINED IN THESE MATERIALS, AND EXPRESSLY DISCLAIMS ALL DIRECT, INDIRECT, SPECIAL, INCIDENTAL, CONSEQUENTIAL, RELIANCE AND PUNITIVE DAMAGES, INCLUDING WITHOUT LIMITATION ANY LOSS OF PROFITS ARISING OUT OF YOUR ACCESS TO, USE OR INTERPRETATION OF, OR ACTIONS TAKEN OR NOT TAKEN BASED ON THE CONTENT OF THESE MATERIALS. Silicon Image, Inc. and its affiliates reserve the right, without notice, to periodically modify the information in these materials, and to add to, delete, and/or change any of this information. Notwithstanding the foregoing, these materials shall not, in the absence of authorization under U.S. and local law and regulations, as required, be used by or exported or re-exported to (i) any U.S. sanctioned or embargoed country, or to nationals or residents of such countries; or (ii) any person, entity, organization or other party identified on the U.S. Department of Commerce's Denied Persons or Entity List, the U.S. Department of Treasury's Specially Designated Nationals or Blocked Persons List, or the Department of State's Debarred Parties List, as published and revised from time to time; (iii) any party engaged in nuclear, chemical/biological weapons or missile proliferation activities; or (iv) any party for use in the design, development, or production of rocket systems or unmanned air vehicles. Products and Services The products and services described in these materials, and any other information, services, designs, know-how and/or products provided by Silicon Image, Inc. and/or its affiliates are provided on as "AS IS" basis, except to the extent that Silicon Image, Inc. and/or its affiliates provides an applicable written limited warranty in its standard form license agreements, standard Terms and Conditions of Sale and Service or its other applicable standard form agreements, in which case such limited warranty shall apply and shall govern in lieu of all other warranties (express, statutory, or implied). EXCEPT FOR SUCH LIMITED WARRANTY, SILICON IMAGE, INC. AND ITS AFFILIATES DISCLAIM ALL REPRESENTATIONS AND WARRANTIES (EXPRESS, IMPLIED, STATUTORY OR OTHERWISE), REGARDING THE INFORMATION, SERVICES, DESIGNS, KNOW-HOW AND PRODUCTS PROVIDED BY SILICON IMAGE, INC. AND/OR ITS AFFILIATES, INCLUDING BUT NOT LIMITED TO, ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND/OR NON-INFRINGEMENT OF THIRD PARTY RIGHTS. YOU ACKNOWLEDGE AND AGREE THAT SUCH INFORMATION, SERVICES, DESIGNS, KNOW-HOW AND PRODUCTS HAVE NOT BEEN DESIGNED, TESTED, OR MANUFACTURED FOR USE OR RESALE IN SYSTEMS WHERE THE FAILURE, MALFUNCTION, OR ANY INACCURACY OF THESE ITEMS CARRIES A RISK OF DEATH OR SERIOUS BODILY INJURY, INCLUDING, BUT NOT LIMITED TO, USE IN NUCLEAR FACILITIES, AIRCRAFT NAVIGATION OR COMMUNICATION, EMERGENCY SYSTEMS, OR OTHER SYSTEMS WITH A SIMILAR DEGREE OF POTENTIAL HAZARD. NO PERSON IS AUTHORIZED TO MAKE ANY OTHER WARRANTY OR REPRESENTATION CONCERNING THE PERFORMANCE OF THE INFORMATION, PRODUCTS, KNOWHOW, DESIGNS OR SERVICES OTHER THAN AS PROVIDED IN THESE TERMS AND CONDITIONS. (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 123 SII0680A PCI to IDE/ATA Data Sheet Silicon Image, Inc. Further Information To request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit the Silicon Image, Inc. web site at www.siliconimage.com. 1060 E. Arques Avenue Sunnyvale, CA 94085 T 408.616.4000 F 408.830.9530 www.siliconimage.com (c) 2006 Silicon Image, Inc. SiI-DS-0069-C 124 |
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